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data sheet 100046c ma r c h 8 , 2000 8223_042 data bus port control 8 8 utopia or fifo interface cell fifo 4-port fifo interface microprocessor interface 52 control registers 28 status registors microprocessor address microprocessor data line overhead 78 8 8 8 8 8 8 16 hdlc data link cell generation tx rate control header filter cell validation cell alignment hec or plcp ds3 e3 (g.751) e3 (g.832) sts-1 e4 (g.832) sts-3c stm-1 taxi framers 1 1 atm layer physical framing atm uni cn8223 atm transmitter/receiver with utopia interface the cn8223 atm transmitter/receiver with utopia level 1 interface provides a single-access atm service termination for user-to-network (uni) and network-to-network interfacing (nni) in conformance with atm forum uni and nni specification 94/0317; bellcore specifications tr-tsv-000772, tr-tsv-000773, tr-nwt-000253, and t1s1/92-185; itu recommendations i.432, g.707, g.751, g.832, and q.921; and etsi prets 300 213 and 300 214. both customer premise equipment (cpe) and switching system interface functions are provided. the cn8223 provides ds1, e1, ds3, e3, e4, sts-1, and sts-3c (and stm-1) atm cell alignment functions. the system interface is via a parallel fifo port or utopia interface. in addition, the cn8223 terminates the operations and maintenance flows f1, f2, and f3. the cn8223 provides four fifo port interfaces and one utopia interface. each receiver port can be programmed with a particular virtual channel identifier/virtual path identifier (vci/vpi) address for message routing. vci/vpi pages can also be selected via masking registers. the microprocessor can set control registers for insertion of selected header fields by the transmitter on an individual port basis. the microprocessor can also control insertion of all overhead and can insert errors in selected fields for test equipment applications. functional block diagram distinguishing features ? integrates 7 line framers with atm layer processing according to atm forum uni and nni specifications utopia level 1 interface internal framers for ds3, e3 (g.751, g.832), e4 (g.832), sts-1, sts-3c, stm-1 plcp and g.804 hec cell alignment for all data rates from 1.544 mbps to 155 mbps direct interface to taxi tm or external t1/e1 framers atm and smds cell modes 4 fifo ports with header screening, formatting, and transmit priority controls idle cells generated and screened statistics counts latched on one-second intervals error detection and insertion option insertion or generation of all line and cell overhead serial or parallel line interface available evaluation module reference design and software supports automatic protection switching (aps) applications wan equipment atm switches test equipment atm routers and hub
100046c conexant ? 1999, 2000, conexant systems, inc. all rights reserved. information in this document is provided in connection with conexant systems, inc. (?conexant?) products. these materials are provided by conexant as a service to its customers and may be used for informational purposes only. conexant assumes no responsibility for errors or omissions in these materials. conexant may make changes to specifications and product descriptions at any time, without notice. conexant makes no commitment to update the information and shall have no responsibility whatsoever fo r conflicts or incompatibilities arising from future changes to its specifications and product descriptions. no license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document. exce pt as provided in conexant?s terms and conditions of sale for such products, conexant assumes no liability whatsoever. these materials are provided ?as is? without warranty of any kind, either express or implied, relating to sale and/or use of conexant products including liability or warranties relating to fitness for a particular purpose, consequential or incidential damages, merchantability, or infringement of any patent, copyright or other intellectual property right. conexant further does not warrant the accuracy or completeness of the information, text, graphics or other items contained within these materials. conexant shall not be liable for any special, indirect, incidental, or consequential damages, including without limitation, lost revenues or lost profits, which may result from the use of these materials. conexant products are not intended for use in medical, life saving or life sustaining applications. conexant customers using or selling conexant products for use in such applications do so at their own risk and agree to fully indemnify conexant for any damages resulting from such improper use or sale. the following are trademarks of conexant systems, inc.: conexant?, the conexant c? symbol, and ?what?s next in communications technologies??. product names or services listed in this publication are for identification purposes only, and m ay be trademarks of third parties. third-party brands and names are the property of their respective owners. for additional disclaimer information, please consult conexant?s disclaimer information posted at www.conexant.com which is incorporated by reference. reader response: conexant strives to produce quality documentation and welcomes your feedback. please send comments and suggestions to conexant.tech.pubs@conexant.com . for technical questions, contact your local conexant sales office or field applications engineer. ordering information part number generic part number operating temperature package description reduced features 28222-13 BT8222EPFE ? 40 c to 85 c 160-pin pqfp ? 28222-14 bt8222epff ? 40 c to 85 c 160-pin pqfp ? 28233-11 cn8223epf ? 40 c to 85 c 160-pin pqfp the cn8223 is based on the bt8222 device. the only change from the bt8222 to the cn8223 is the ttl i/o pad ring. the i/o structure allows the cn8223 to function in a 3.3/5 v environment. no new features, errata fixes, etc., have been added to the cn8223 other than ttl threshold inputs.
10046c conexant iii table of contents list of figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . vii list of tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix 1.0 product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.1 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 1.2 cn8223 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.1 internal framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.2 utopia port . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-3 1.2.3 programmable parity protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.4 test and diagnostic functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.2.5 microprocessor interface features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4 1.3 line framing functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 1.3.1 interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.2 line loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6 1.3.3 bip-8 code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.3.4 alarm detection/generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-7 1.4 atm cell processing functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 1.4.1 cell generation functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.2 tx rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.4.3 cell validation functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-9 1.5 fifo port/utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.1 utopia mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.2 fifo ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-10 1.5.3 atm interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-11 1.6 line interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 1.7 cn8223 versions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 1.8 cn8223 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 1.8.1 cn8223 as a ds3 or e3 g.751 framer without atm cell delineation . . . . . . . . . . . . . . . . 1-16 1.9 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-17 1.10 pin definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19
table of contents cn8223 atm transmitter/receiver with utopia interface iv conexant 100046c 2.0 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 2.1 microprocessor interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.1 8/16-bit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.1.2 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2 2.2 line framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -3 2.2.1 internally framed transmit line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 2.2.1.1 high-speed pecl transmit interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-5 2.2.2 internally framed receive line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 2.2.2.1 high-speed pecl receive interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.2.2 receiver framing operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 2.2.3 externally framed transmit line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 2.2.4 externally framed receive line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 2.3 overhead generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.1 internal ds3 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 2.3.2 internal g.832 e3/e4 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.3 internal g.751 e3 mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 2.3.4 sts-1 and sts-3c/stm-1 modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 2.3.5 transmit framing overhead interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 2.3.6 receive framing overhead interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 2.4 status and alarms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.1 status and counter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-19 2.4.2 alarm signal generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-20 2.4.3 alarm detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 2.5 parallel line interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.5.1 taxi interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-22 2.5.2 transmit parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 2.5.3 receive parallel interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 2.6 atm cell processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.6.1 cell generation for transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-26 2.6.1.1 cell_gen_x register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 2.6.1.2 cell generation status and status interrupts for transmit . . . . . . . . . . . . . . . 2-28 2.6.2 cell validation for receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-29 2.6.2.1 hec alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.6.2.2 cell_val control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-30 2.6.2.3 interrupts and status counters for cell validation . . . . . . . . . . . . . . . . . . . . . 2-32 2.6.3 plcp cell generation for transmit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-33 2.6.4 plcp cell validation for receive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.6.4.1 plcp status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-35 2.6.5 plcp transmit/receive synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-36
cn8223 table of contents atm transmitter/receiver with utopia interface 100046c conexant v 2.7 fifo port/utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.7.1 fifo interface inputs and outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 2.7.2 transmit port priority mechanism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 2.7.3 transmit rate shaping control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.7.4 receive port addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-41 2.7.4.1 header screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.7.4.2 output screening . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-42 2.7.5 utopia interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 2.8 feac channel and hdlc data link programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.8.1 feac channel transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-44 2.8.2 feac channel receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.8.3 hdlc data link transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-45 2.8.3.1 sending a message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-46 2.8.3.2 aborting a message . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.8.3.3 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-47 2.8.3.4 transmitter control example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 2.8.4 hdlc data link receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-48 2.8.4.1 receiver operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-49 2.8.4.2 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-50 2.8.5 receiver response example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-51 3.0 registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.1 registers overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-1 3.2 control register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 3.3 configuration control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 0x00 ? config_1 (configuration control register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-4 0x01 ? config_2 (configuration control register 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-7 0x02 ? config_3 (configuration control register 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-9 0x29 ? config_4 (configuration control register 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-10 0x31 ? config_5 (configuration control register 5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-11 0x2b ? utopia_1 (utopia port control register 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-12 0x2c ? utopia_2 (utopia port control register 2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-13 3.4 transmit control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 0x03 ? txfeac_errpat (transmit feac/error pattern register) . . . . . . . . . . . . . . . . . . . . . . . . . 3-14 0x60 ? dl_ctrl_stat (hdlc data link control and status register) . . . . . . . . . . . . . . . . . . . . . 3-15 0x04 ? 0x07 ? cell_gen_x (cell generation control registers) . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 0x08 ? tx_rate_23 (transmit rate control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 0x09 ? tx_rate_01 (transmit rate control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 0x0a ? tx_idle_12 (transmit idle header register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 0x0b ? tx_idle_34 (transmit idle header register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-17 0x2a ? idle_pay (transmit idle cell payload register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-18 0x0c ? 0x13 ? tx_hdrx_12, tx_hdrx_34 (transmit header registers) . . . . . . . . . . . . . . . . . . . . 3-18
table of contents cn8223 atm transmitter/receiver with utopia interface vi conexant 100046c 3.5 receive control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 0x14 ? cell_val (cell validation control register) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19 0x15 ? 0x1c ? hdr_valx_12, hdr_valx_34 (receive header value register) . . . . . . . . . . . . . . . 3-21 0x1d ? 0x24 ? hdr_mskx_12, hdr_mskx_34 (receive header mask register) . . . . . . . . . . . . . . 3-22 0x25, 0x26 ? rx_idle_12, rx_idle_34 (receive idle header registers) . . . . . . . . . . . . . . . . . . . 3-23 0x27, 0x28 ? idle_msk_12, idle_msk_34 (receive idle header mask register) . . . . . . . . . . . . 3-23 3.6 interrupt enable control registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 0x2d ? en_line_int (enable line interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24 0x2e ? en_event_int (enable event interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25 0x2f ? en_ovfl_int (enable overflow interrupts). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-26 0x30 ? en_cell_int (enable cell interrupts) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 0x32 ? tx_k1k2 (transmit k1 and k2 value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 0x33 ? rx_k1k2 (receive k1 and k2 value) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-27 3.7 status register overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-28 0x38 ? line_status (line framer/phy interrupt status register) . . . . . . . . . . . . . . . . . . . . . . . . 3-29 0x39 ? event_status (event interrupt status register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-36 0x3a ? ovfl_status (counter overflow interrupt status register) . . . . . . . . . . . . . . . . . . . . . . . 3-37 0x3b ? cell_status (interrupt status register). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-38 0x3c ? rxfeac_ver (receive feac/part number/version number register) . . . . . . . . . . . . . . . . 3-38 3.8 event/error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-39 4.0 electrical and mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.1 power requirements and temperature range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 4.2 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2 4.3 timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.1 microprocessor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 4.3.2 line interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-6 4.3.3 fifo interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 4.3.4 utopia interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 4.3.5 taxi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 4.4 mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-17 appendix a:transmit fifo port rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.1 rate control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-1 a.2 port priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 a.3 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-2 appendix b:acronym list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . b-1
cn8223 list of figures atm transmitter/receiver with utopia interface 100046c conexant vii list of figures figure 1-1. cn8223 detailed block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-2 figure 1-2. line framer diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5 figure 1-3. cn8223 cell processing block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-8 figure 1-4. fifo port/utopia interface block . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-10 figure 1-5. line interface applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-12 figure 1-6. cn8223 connected to cat 5 or pmd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-14 figure 1-7. cn8223 connected to bt8360 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-14 figure 1-8. cn8223 connected to bt8510 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15 figure 1-9. cn8223 connected to bt8370 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1-15 figure 1-10. cn8223 connected to tdk 78p7200. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-1 6 figure 1-11. cn8223 logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-18 figure 1-12. cn8223 pinout diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-19 figure 2-1. cn8223 receiver block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-1 figure 2-2. cn8223 transmitter block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-1 figure 2-3. internal framer transmitter interface timing with line encoding . . . . . . . . . . . . . . . . . . . . 2-4 figure 2-4. internal framer transmitter interface timing without line encoding . . . . . . . . . . . . . . . . . 2-5 figure 2-5. internal framer receiver interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 figure 2-6. timing for internal framer receiver, encoder disabled . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-7 figure 2-7. ds1 interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 figure 2-8. e1 interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9 figure 2-9. ds3 interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-10 figure 2-10. e3 interface transmit timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 figure 2-11. receiver ds1 line interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-12 figure 2-12. transmit framing overhead interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-17 figure 2-13. receive framing overhead interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-18 figure 2-14. transmit parallel interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-24 figure 2-15. receive parallel interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 figure 2-16. transmit fifo port interface timing, 53-octet mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-38 figure 2-17. receive fifo port interface timing, 53-octet mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-39 figure 3-1. line_status and oof example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-2 9 figure 3-2. register summary, cheat sheet 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-46 figure 3-3. register summary, cheat sheet 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-47 figure 4-1. local processor interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-5 figure 4-2. line interface timing ? ds1, e1, ds3, e3 external framers . . . . . . . . . . . . . . . . . . . . . . . . 4-7 figure 4-3. line interface timing ? internal framers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 figure 4-4. parallel interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 figure 4-5. overhead port interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-10
list of figures cn8223 atm transmitter/receiver with utopia interface viii conexant 100046c figure 4-6. fifo port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-12 figure 4-7. utopia interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-14 figure 4-8. taxi port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-16 figure 4-9. cn8223 160-pin plastic quad flat pack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-1 7
cn8223 list of tables atm transmitter/receiver with utopia interface 100046c conexant ix list of tables table 1-1. cn8223 version descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-13 table 1-2. hardware signal definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-20 table 2-1. valid config_1 line mode settings, bits 7 ? 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 table 2-2. internal framer transmitter interface connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4 table 2-3. internal framing unencoded transmitter connections (sts-3c, stm-1, e4) . . . . . . . . . . . 2-5 table 2-4. internal framer receiver interface connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-6 table 2-5. connections for internal framer rx, encoder disabled (sts-3c, stm-1, e4) . . . . . . . . . . . 2-7 table 2-6. serial external framer transmitter interface connection . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-8 table 2-7. external framing mode receiver connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-11 table 2-8. ds3 overhead values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-13 table 2-9. g.832 e3 and e4 overhead values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2- 14 table 2-10. g.751 e3 overhead values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-14 table 2-11. c1 values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-12. sts-1, sts-3c, and stm-1 overhead values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-15 table 2-13. status indications for all modes (register 0x38) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-21 table 2-14. pin connections between taxi chipset and cn8223 . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 table 2-15. transmit parallel interface mode connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-23 table 2-16. receive parallel interface mode connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-25 table 2-17. cell generation modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-27 table 2-18. overhead field locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-28 table 2-19. status octet definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-31 table 2-20. pt header field and user data bit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2-31 table 2-21. febe controls . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 table 2-22. c1 octet . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-34 table 2-23. fifo interface pin connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-37 table 2-24. fifo transmit pin functional descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-3 9 table 2-25. fifo receive pin descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 table 2-26. priority levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-40 table 2-27. utopia interface pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-43 table 2-28. byte transmission times for transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 -46 table 3-1. atm transmitter/receiver status registers, counters, and data link control . . . . . . . . . . 3-1 table 3-2. atm transmitter/receiver microprocessor control registers . . . . . . . . . . . . . . . . . . . . . . . 3-2 table 3-3. valid combinations of config_1, bits 0 ? 7 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-6 table 3-4. alarm transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 table 3-5. alarm transmission ? sts ? 1/sts ? 3c/stm ? 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 table 3-6. overhead generation disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-8 table 3-7. cell_gen_x control register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-16 table 3-8. tx_hdrx register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3-18 table 3-9. hdr_valx register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -21
list of tables cn8223 atm transmitter/receiver with utopia interface x conexant 10046c table 3-10. hdr_mskx register addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -22 table 3-11. atm transmitter/receiver status registers, counters, and data link control . . . . . . . . . 3-28 table 3-12. sts-1,sts-3c, stm-1 line_status bit definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-30 table 3-13. ds3 plcp and direct mapping mode line_status bit definitions. . . . . . . . . . . . . . . . . 3-31 table 3-14. e3 g.832, e4 g.832 line_status bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-32 table 3-15. e3 g.751 line_status bit definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-3 3 table 3-16. external framer, 57-octet mode, line_status bit definitions . . . . . . . . . . . . . . . . . . . . 3-34 table 3-17. status indications for all modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-35 table 3-18. line and interface events/errors counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3- 39 table 3-19. counted events . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-40 table 3-20. internal sts-1, sts-3c event/error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-41 table 3-21. internal ds3 plcp and direct mapping modes event/error counters. . . . . . . . . . . . . . . . 3-42 table 3-22. internal g.832 e3/e4 event/error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-43 table 3-23. internal g.751 e3 event/error counters. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 -44 table 3-24. external framer, 57-octet mode event/error counters . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-45 table 4-1. dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-3 table 4-2. microprocessor interface timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-4 table 4-3. line interface timing ? ds1, e1, ds3, e3 external framers . . . . . . . . . . . . . . . . . . . . . . . . 4-6 table 4-4. line interface timing ? internal framers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-7 table 4-5. parallel interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-8 table 4-6. overhead port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-9 table 4-7. fifo port interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-11 table 4-8. utopia interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-13 table 4-9. taxi interface timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-15 table a-1. cell thresholds (1 of 4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . a-3
100046c conexant 1-1 1 1.0 product description the cn8223 atm physical interface (phy) device is a transmitter/receiver which converts several types of frames to atm cells and vice versa. the device contains framers for ds3, e3, e4, sts-1, sts-3c, and stm-1. this chapter provides an overview of the cn8223, describing its primary features and applications. a block diagram and a logic diagram are included. 1.1 block diagram figure 1-1 is a detailed block diagram of the cn8223. the host system transmits octet-wide data to the cn8223 via the utopia or fifo ports. this data is assembled into atm cells by the phy and formatted for serial line transmission by the cn8223?s line framers. in the receive direction, serial network data is framed into octets by either internal or external line framers and passed to the atm cell processing block. octet data is then aligned into atm cells, checked, and sent through the utopia or fifo ports to the host system. the line framer block connects to external interfaces for line reception and transmission. the line framer has interfaces for seven data rates and provisions for external serial or parallel framers. also included are overhead interfaces, data links, and event counters. the hec/plcp atm cell alignment block accepts octet data from the line framer block. it generates cells for transmission and validates received cells. included are hec/plcp generators and detectors, data scramblers, and counters. the fifo port/utopia interface communicates with the next layer of atm processing, usually residing in the host system. it directs received cell traffic to four ports, controls transmit priority and rate, and has counters for events and errors.
1.0 product description cn8223 1.1 block diagram atm transmitter/receiver with utopia interface 1-2 conexant 100046c figure 1-1. cn8223 detailed block diagram port 1 ctrl port 2 ctrl port 3 ctrl utopia ctrl port 0 ctrl ds3, e3, e4, sts-1 sts-3c, stm-1 g.832 transmit framer ds3, e3, e4, sts-1 sts-3c, stm-1 g.832 receive framer microprocessor interface transmit g.832 and plcp framer rx hdlc tx feac tx hdlc tx cell generation, tx rate and priority rx cell validation rx vpi/vci screening 4-port fifo data interface 9 9 tx overhead insert rx overhead extract line interfaces 9 9 parallel interface high speed medium speed 8 rxovh txovh rmrkr rovh_clk tmrkr tovh_clk a[7:1] prclk cs~ as~ w/r~ oe~ sel8bit fdat_in fdat_out fctrl_out[16:0] tclko_hs tclko txout[7:0] rcv_hld clock and control oneseci 8kcki ntest test1, 3 reset line framer section cell processing section fifo data ports section 16 txout_hs txcki_hs rxcki_hs rxin_hs txout txcki rxcki rxin locd rxin[7:0] receive g.832 and plcp framer 8 utopia interface and 4-cell buffers rx feac 8 fctrl_in[7:0] cell counters performance monitoring interrupt control cn8223 dl_int stat_int d[15:0] oneseco 8223_001
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.2 cn8223 features 100046c conexant 1-3 1.2 cn8223 features the cn8223 atm transmitter/receiver provides a single-access atm service termination for uni and nni. it conforms to the following specifications and recommendations: atm forum uni specification 94/0317 bellcore specifications tr-tsv-000772, tr-tsv-000773, tr-nwt-000253, and t1s1/92-185 itu recommendations i.432, g.707, g.751, g.832, and q.921 etsi draft standards prets 300 213 and 300 214 both terminal and switching system interface functions are provided. the cn8223 provides ds1, e1, ds3, e3, e4, sts-1, and sts-3c (stm-1) physical layer convergence procedure (plcp) functions. it optionally provides for the generation and validation of aal3/4 and aal5 atm cell payloads. the system interfaces to the atm layer through either a utopia-compatible port or a parallel fifo port. provisions for source rate control are included in the transmitter circuitry. 1.2.1 internal framers internal framers are included for ds3 c-bit parity format, g.751 e3 format, g.832 e3 and e4 formats, and sts-1/sts-3c/stm-1 formats. cell delineation is via either plcp framing overhead or g.832 header error control (hec) alignment. the cn8223 parallel line interface allows octet recovery/transmission externally for 100 mbps taxi or other interfaces. the ds1, ds3, e1, and e3 data stream interfaces connect directly to conexant framers (bt8360c for ds1, bt8510b for e1, bt8370 for e1/t1 with integral line interface unit (liu), and bt8330b for ds3 and e3). ds1 and ds3 plcp functions conform to bellcore standard tr-tsv-000773; e1 plcp conforms to etsi draft standard prets 300 213; and e3 plcp conforms to etsi draft standard prets 300 214. transmit and receive functions are provided for all line rates up to 155 mbps. 1.2.2 utopia port the utopia port conforms to the atm forum utopia level 1 specification (version 2.01) and provides both octet- and cell-based handshaking. the interface contains transmit and receive buffer fifos with a depth of four cells programmable for reduced latency requirements per atm forum document 94/0317. this interface conforms to the saturn compliant interface for atm phy devices specification. the microprocessor can set control registers for insertion of selected header fields by the transmitter on an individual port basis. also, the processor can control insertion of all overhead and can insert errors in selected fields for test equipment applications.
1.0 product description cn8223 1.2 cn8223 features atm transmitter/receiver with utopia interface 1-4 conexant 100046c 1.2.3 programmable parity protection programmable parity protection is available on the system interface. read and write strobes allow addressing of up to four distinct data sources and output to four distinct destinations. each transmitter port has a programmable priority level. if the priority levels are the same, the ports are addressed in sequence. each receiver port can be programmed with a particular vci/vpi address for message routing. also, vci/vpi pages can be selected via masking registers. cells can be routed to multiple ports for broadcast capability and enhanced test, diagnostic, and maintenance functions. also, the cell validation function can be programmed to correct single-bit header errors. 1.2.4 test and diagnostic functions the cn8223 provides access to the atm protocol at all levels for test and diagnostic functions. octet-wide simultaneous interfaces are provided for transmit and receive access to plcp slots (57 octets), atm cells (53 octets), cells without hec (52 octets), or cell payload only (48 octets). this interface allows the implementation of test and diagnostic systems. also, per-cell status can be optionally provided in place of the hec octet on port 3 in a special output mode. 1.2.5 microprocessor interface features all control and status functions are provided via a direct microprocessor interface. also, the microprocessor can control the external framers as required. the microprocessor interface can be used with either an 8- or 16-bit data bus with separate address and data signals. interrupt outputs are provided for status information on cell and physical layer performance and for data link operations. the interface is a clocked 8- or 16-bit data interface with an address strobe and a single read/write control.
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.3 line framing functions 100046c conexant 1-5 1.3 line framing functions the cn8223 provides framers for ds3, e3 (both g.751 and g.832), e4 (g.832), sts-1, and sts-3c/stm-1 formatted serial streams. the line receive circuitry recovers the frame location from the serial stream and provides cell octets to the physical layer block for cell delineation. the transmit circuitry receives cell octets from the cell generation or physical layer blocks and adds line framing overhead information as required. the liu receive interface detects both loss-of-signal (los) and line code violations (lcvs). the active edge of the transmit output clock is selectable. figure 1-2 illustrates the line framer functions of the cn8223. cn8223 line framing functions include the following: sts-1, sts-3c, stm-1, ds3, e3, e4, taxi external framer interface parallel interface unframed serial interface hdb3/b3zs encode/decode line overhead insertion/extraction sonet scrambling error insertion alarm detection/generation figure 1-2. line framer diagram ds3, e3, e4, sts-1 sts-3c, stm-1 transmit framer ds3, e3, e4, sts-1 sts-3c, stm-1 receive framer rx hdlc tx feac tx hdlc tx overhead insert rx overhead extract line interfaces 9 9 parallel interface high speed medium speed 8 txovh tmrkr tovh_clk tclko_hs tclko txout[7:0] rcv_hld txout_hs txcki_hs rxcki_hs rxin_hs txout txcki rxcki rxin locd rxin[7:0] rx feac rmrkr rovh_clk 8 rxovh cn8223 cell processing 8223_002
1.0 product description cn8223 1.3 line framing functions atm transmitter/receiver with utopia interface 1-6 conexant 100046c 1.3.1 interfaces the cn8223 has a serial external framer interface for t1, e1, t3, and e3. the internal b3zs/hdb3 encoder/decoder can be bypassed in any mode for direct input/output of nrz data and clock. the line signal interface consists of clock, serial or octet data, and sync signals from either the internal or external framers. both framed and unframed modes are usable at ds1, e1, ds3, and e3 line rates. in framed mode, the frame/overhead bit positions of the transmission format are located through a synchronization signal and are generated as idle bits or ignored. in unframed mode, a serial signal that contains no line overhead bit positions is expected. the transmitter interface has a clock signal input and provides a serial or octet data output. the receive signal interface consists of input clock and serial or octet data from the transmission physical layer framer. also, synchronization inputs are provided for use with external framers. the transmit and receive sections of the interface are clocked independently. a parallel line interface is available for external framers and other devices. it consists of a receive clock and octet and a transmit clock and octet. this interface permits clocking externally recovered octets directly to and from the cell delineation function block. use of the parallel interface assumes all line overhead information has been removed externally and proper octet alignment has been recovered. 1.3.2 line loopback a line loopback connects the receive clock and data inputs directly to the transmit clock and data outputs. lcvs are preserved in this loopback. raw yellow alarm indications and out-of-frame (oof) events are integrated to provide yellow alarm and loss-of-frame (lof) indications, respectively. phy error counters can be programmed to accumulate errors over one-second periods and latch the results. line framing functions are described in detail in section 2.2 .
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.3 line framing functions 100046c conexant 1-7 1.3.3 bip-8 code the octet bit interleaved parity (bip-8) code is checked and error status generated for the far end block error (febe) function and yellow alarm. bip-8 code violations and framing-octet errors are counted. oof events are detected and counted. the transmitter output can be looped to the receiver input for test purposes and to perform startup self-tests and diagnostics. in all phy modes, an oof input from the internal or external framer can be used to indicate that the received signal is not being received correctly. this input inhibits cell validation functions and initiates cycle stuffing, when required. 1.3.4 alarm detection/generation all line alarm and error conditions including bip codes are monitored and reported in status registers and event counters. alarms and errors can be configured to generate an interrupt to the microprocessor. the cn8223 can transmit alarm and error conditions under microprocessor control.
1.0 product description cn8223 1.4 atm cell processing functions atm transmitter/receiver with utopia interface 1-8 conexant 100046c 1.4 atm cell processing functions figure 1-3 illustrates the cn8223 cell processing block, which assembles received octet data from the line framers into atm cells. during transmit, this block constructs atm cells for the line transmitter circuits. the atm cell processing block can generate or receive either the 57-octet framed plcps or the 53-octet direct-mapped formats. status indications include 16-bit counters for plcp oof or loss-of-cell (loc) delineation events, framing-octet errors, and bip-8 code violations for both the near and far end. all alarm indications are provided and can be programmed to generate interrupts. cn8223 cell processing block features include the following: selectable hec or plcp alignment hec calculation for atm or smds hec correction hec coset generation plcp overhead control plcp events and alarms control aal3/4 crc and length check support sonet scrambling atm payload scrambling error insertion figure 1-3. cn8223 cell processing block transmit g.832 and plcp framer tx cell generation, tx rate and priority rx cell validation rx vpi/vci screening receive g.832 and plcp framer fifo/utopia ports block line framers block 8223_003
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.4 atm cell processing functions 100046c conexant 1-9 1.4.1 cell generation functions the cn8223 atm cell processing block provides flexible control for cell generation. cell generation is the formatting of 48-octet payload segments into 53-octet atm cells, and the generation of appropriate header octets, hec, and payload cyclic redundancy check (crc) calculations as required by the aal formats. the cn8223 provides modes that perform this cell generation function, along with modes that allow insertion of any or all of the various header fields from either the fifo interface or from microprocessor control registers. four cell generation modes are available in the cn8223. cell generation functions are described in detail in section 2.6 . 1.4.2 tx rate control two rate control registers [0x08, 0x09] are provided for each of the four ports to allow programmable rate shaping of cell transmission. the ratio of active to idle cells is programmable with 0.4 % granularity. status counts of non-idle cells transmitted are maintained for each of the four sources. 1.4.3 cell validation functions cell validation refers to the checking of cells coming in from the phy block for proper format. the cn8223 provides modes that deliver 48-, 52-, or 53-octet cells, or 57-octet plcp slots to the fifo output ports. the validation process is described in detail in section 2.6 . protocol verification includes hec validation with atm or smds/802.6 coverage, validation of payload length per segment type, and correct payload crc value. status reporting of validation steps is via error counters and status register indications. status bits can be programmed to generate interrupts to the microprocessor. each validation step can be individually disabled.
1.0 product description cn8223 1.5 fifo port/utopia interface atm transmitter/receiver with utopia interface 1-10 conexant 100046c 1.5 fifo port/utopia interface the cn8223 fifo port/utopia interface is the data connection for the host system. figure 1-4 illustrates the functions in this block. this block has two modes for interfacing with atm cells: four fifo ports or one atm forum level 1 compliant utopia port. fifo port/utopia interface block features include the following: four byte-wide fifo ports utopia port with four-cell buffer port rate and priority control idle cell tx/rx per-port atm header screening 48-, 52-, 53-, and 57-octet cell modes 1.5.1 utopia mode utopia mode implements a single 25 mhz, 8-bit plus parity bidirectional interface with four cells of internal fifo in both directions. parity is optional. when the utopia interface mode is used, only 53-octet output is available. 1.5.2 fifo ports cells are routed to one of four output ports if a match to that port ? s programmable header value is made. this can be used to route received vci/vpis to a chosen port. four modes are available for fifo port cell output: a test mode writes the entire 57-octet plcp slot to the fifo interface. a 53-octet mode writes the 53-octet atm cell to the fifo interface. a 52-octet mode writes the atm cell without the hec octet to the fifo interface. a final mode delivers 48-octet cell payloads to the fifo interface. figure 1-4. fifo port/utopia interface block port 1 ctrl port 2 ctrl port 3 ctrl utopia ctrl port 0 ctrl rx vpi/vci screening 4-port fifo data interface 9 9 fdat_in fdat_out fctrl_out[16:0] utopia interface and 4-cell buffers fctrl_in[7:0] atm cell processing block atm layer cell processing fifo 8223_004
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.5 fifo port/utopia interface 100046c conexant 1-11 1.5.3 atm interface each cell is sent to a buffer to allow for header processing before being output to the atm interface. the buffer length is 10 octets for g.751 plcp modes, and 6 octets for hec alignment. a ? cell-valid ? output is provided to indicate that none of the enabled error checks detected an error. the utopia internal fifo or external circuitry is notified to discard the cell when the valid indication goes inactive. idle cells are automatically deleted from the atm layer output. parity and control/delineation signals are provided with each octet at the port interface. the microprocessor receives status and error counts as cell validation proceeds. all event and error counters can be programmed to cause an interrupt on overflow. reading the interrupt source register allows the microprocessor to identify overflows and thus update internal counts. all counters can be read by the microprocessor and are cleared when read.
1.0 product description cn8223 1.6 line interface applications atm transmitter/receiver with utopia interface 1-12 conexant 100046c 1.6 line interface applications with minimal glue logic, the cn8223 provides interfaces to sts-3c, stm-1, ds3, e3, taxi, ds1, or e1 equipment. multiple line rates can be supported with a single design if the line interface is on a daughter card. figure 1-5 illustrates the configuration for several line interfaces. figure 1-5. line interface applications 8223_005 clock recover optical transceiver sts-3c, stm-1 interface cn8223 signal names ds3, e3 interface sonet fiber line transformer line interface unit chip copper line amd taxi chipset optical or electrical interface fiber or copper taxi interface line transformer bt8360 or bt8510 or bt8370 ds1 or e1 interface copper line cn8223 external framer serial interface cn8223 low-speed serial line interface cn8223 external framer parallel interface cn8223 high-speed serial line interface txcki, tclko, txpos, txneg, rxcki, rxpos, rxneg, rxlos txcki_hs+/ ? , tclko_hs+/ ? , txout_hs+/ ? , rxcki_hs+/ ? , rxin_hs+/ ? txcki, txin, txout[3], rxcki, rxin[0,3,4] txcki, tclko, txin, txout[8:0], rxcki, rxin, txout[8:0], rcv_hld
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.7 cn8223 versions 100046c conexant 1-13 1.7 cn8223 versions table 1-1 describes the revision history of the bt8222 device. the bt8222 is the predecessor of the cn8223. table 1-1. cn8223 version descriptions version description bt8222kpf baseline version (derived from the bt8220/1). bt8222kpfb all bt8222kpf functionality plus: the version number was changed to 62h in the lower byte of the rx_feac_ver register. a software reset was added to config_5, bit 7. when active high, this is a software equivalent to pin 118. additional overhead insertion capability for sts-3c, stm-1: g1, k2 #1, and z2 #3 can be inserted from the external overhead bus. it is controlled by config_3, bit 6. this is used for automatic protection switching. config_5 has a new receive status indication. config_5, bit 9 now shows octet g1, bit 5 of received frames. bt8222kpfc all bt8222kpfb functionality plus: the version number was changed to 63h in the lower byte of the rx_feac_ver register. the stm-1 c2 transmit octet = 0x13. the c2 receive octet is checked for 0x01 or 0x13. bt8222kpfd or bt8222epfd all bt8222kpfc functionality plus: the version number was changed to 64h in the lower byte of the rx_feac_ver register. taxi command strobe timing eliminates the need for an external buffer. the g1 octet complies with t1.105. the rdi alarm includes bit 7. the k1/k2 registers were added to provide further support for sonet aps. hec integration was removed. the device complies with a footnote in the utopia specification that allows rxenb~ to be permanently asserted by the atm layer. disable hec check (bit 9 in cell_val) was changed when in utopia mode to be consistent with fifo mode. payload checking will comply with the atm standards (lengths 8-44). when switching to plcp mode dynamically, the device will go to an oof state. fifo read strobes are forced inactive (high) during hardware or software resets. BT8222EPFE all bt8222kpfd/epfd functionality plus: rmrkr[1] was changed to be an 8 khz output synchronized to the received plcp frame. bt8222epff all BT8222EPFE functionality plus: line loopback (bit 9) in the config_3 register (0x02) is cleared upon assertion of reset (pin 118). receive sts/sdh pointer processing complies with standards. legend for version numbers: k = temperature range 0 c to 70 c e = ? 40 c to 85 c pf = package code = 160-pin pqfp a/b/c/d/e = product version
1.0 product description cn8223 1.8 cn8223 applications atm transmitter/receiver with utopia interface 1-14 conexant 100046c 1.8 cn8223 applications the cn8223 can be connected to several types of framers and pmds. figure 1-6 illustrates a general application where the cn8223 is connected to either a cat 5 or fiber optic pmd. figure 1-7 illustrates an example implementation of the cn8223 using a bt8360 external t1 framer. figure 1-6. cn8223 connected to cat 5 or pmd utopia cn8223 cat 5 utp utopia rxdata rxclk loss of signal txdata raw rd 19.44 mhz rx bus tx bus clock recovery control bus circuit oscillator or fiber module transceiver (pe-68532g or pulse engineering (sumitomo (analog devices pe-68538g) sdm 4201-xc) ad6116) or (cypress cx7b952) semiconductor txclk 8223_006 figure 1-7. cn8223 connected to bt8360 rx rxin[0] txout[3] rxin[4] txcki rxcki txin rxin[3] cn8223 liu tx tx data rx data derived cells atm rcko/slcki rfsyo/slfsyo slsyi xbcki pin pin pin txcki txsyi txdato rxcki rxsyi rxlos* signal 30 32 36 10 18 15 19 43 27 30 37/49 38/41 36/55 50 29 63 62 61 7 6 8 rposi rnegi rcki xposo xnego xcko xbsfsyo xcki xpcmi system clock tx clock layer bt8360 rxdati rpcmo/slpcmo 8223_007
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.8 cn8223 applications 100046c conexant 1-15 figure 1-8 illustrates an example implementation of the cn8223 using a bt8510 external e1 framer. figure 1-9 illustrates an example implementation of the cn8223 using a bt8370 external t1/e1 framer. figure 1-8. cn8223 connected to bt8510 rx rxin[0] txout[3] txcki rxcki txin rxin[3] cn8223 8223_008 tx cells atm rsynco rpcmo pin pin txcki txsyi t x pato rxcki rxsyi signal 30 32 36 10 18 15 27 30 37 38 36 29 xsynco xcki xpcmi system clock layer rcko bt8510 rxdati figure 1-9. cn8223 connected to bt8370 rx rxin[0] txout[3] txcki rxcki txin rxin[3] cn8223 8223_009 tx cells atm rmsync rpcmo pin pin txcki txsyi t x pato rxcki rxsyi signal 30 32 36 10 18 15 36 34 48 44 42 64 37 tmsync tcki tsbcki tpcmi system clock layer rcko bt8370 rxdati
1.0 product description cn8223 1.8 cn8223 applications atm transmitter/receiver with utopia interface 1-16 conexant 100046c figure 1-10 illustrates an example implementation of the cn8223 using a tdk 78p7200 t3 liu. unused pins on the cn8223 must be tied as follows: unused rxin_8:0 pins tie to ground, pecl inputs rxcki_hs, rxin_hs, and txcki_hs tie to +5 v. 1.8.1 cn8223 as a ds3 or e3 g.751 framer without atm cell delineation the cn8223 can be used as a ds3 or an e3 g.751 framer with parallel input and serial output by making the following changes: set the configuration registers for transparent operation. disable the parallel interface. disable line loopback. in this setup, the receive frame sync pulse is on pin 43, txout[5]. data is received on pin 56, txout[6]. the receive clock is derived from the liu device. data is transmitted through the parallel utopia interface. figure 1-10. cn8223 connected to tdk 78p7200 rx rxin[4] txcki txout[1] rxcki tclko rxin[2] txout[2] rxin[1] cn8223 8223_010 tx cells atm rpos lowsig pin pin signal 31 35 34 10 17 16 19 30 14 23 24 25 27 15 27 tpos tneg tclk rclk system clock (44.736 mhz) layer rneg tdk 78p7200
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.9 logic diagram 100046c conexant 1-17 1.9 logic diagram the cn8223 is a single cmos integrated circuit, packaged in a 160-pin plastic quad flat pack (pqfp). figure 1-11 illustrates a cn8223 logic diagram. the line framer/phy interface consists of 33 pins. the framing overhead interface consists of 22 pins. the fifo interface consists of 18 data pins, 8 control inputs, and 17 control outputs. the microprocessor interface consists of 8 clock and control inputs, a 16-bit data bus, a 7-bit address bus, and 2 interrupt outputs. additionally, there are 11 power and 12 ground pins. detailed pin descriptions are given in table 1-2 . clock and control inputs consist of an external 8 khz reference for the plcp at e3 and ds3 rates, a one-second input to synchronize status collection timing in multiple-port applications, a ? hold receiver ? input that can externally disable cell validation when an external framer loses frame or signal, three test inputs, and a reset input. a one-second clock output is provided to allow synchronization of status collection for multiple cn8223s or for cn8223s and framers. when a single cn8223 is used, oneseco should be connected to oneseci. this timing output is derived from the external 8 khz reference clock input on 8kcki. an 8 khz clock from the line receiver is available on rmrkr[1], pin 8. note: rmrkr[1] is not available in ds-3 direct cell mapping mode.
1.0 product description cn8223 1.9 logic diagram atm transmitter/receiver with utopia interface 1-18 conexant 100046c figure 1-11. cn8223 logic diagram receive clock input receive clock in pecl receive serial in pecl receive input transmit clock input transmit clock in pecl transmit input transmit overhead fifo data bus in fifo control input 8 khz clock input one-second clock sync receiver hold input test input reset processor clock chip select address strobe write/read control output enable processor data bus address bus 8/16-bit mode select test inputs bus in 98 ? 105, 108 109 ? 116 microprocessor transmit clock output transmit outputs transmit clock out pecl transmit serial out pecl loss of cell delineation rxcki rxcki_hs rxin_hs rxin[8:0] tclko txout[8:0] tclko_hs txout_hs locd line framer/phy interface i i i i txovh[7:0] i txcki txcki_hs txin i i i o o o o o framing overhead interface o o o receive overhead bus out receive overhead markers receive overhead clocks transmit overhead clock transmit overhead marker o o rxovh[7:0] rmrkr[1:0] rovh_clk[1:0] tovh_clk tmrkr fdat_in[8:0] fctrl_in[7:0] i i utopia/fifo interface fdat_out[8:0] fctrl_out[16:0] o o fifo data bus out fifo control outputs interface i i i i i i/o prclk cs ~ as ~ w/r ~ oe ~ d[15:0] a[7:1] i dl_int stat_int o o feac/hdlc interrupt status/counter interrupt 8kcki oneseci rcv_hld ntest reset i i i i i clock and control o one-second output oneseco 15 ? 19, 154,155 22,25 10 11,12 20,21 30 31 33 ? 36, 42,43, 56 ? 58 28,29 38,39 122 156 ? 159 2 ? 5, 8,9 6,7 23,24 32 44 ? 51 i 37 sel8bit 97 96 94 95 92 65, 82 ? 84 85 ? 91 62 61 123 59 119 118 55 52 143 ? 145, 148 ? 153 124 ? 132, 135 ? 142 63 64 60 68 ? 79, test1, test3 i 117, i = input, o = output 8223_011
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.10 pin definitions 100046c conexant 1-19 1.10 pin definitions figure 1-12 is a pinout diagram for the 160-pin atm transmitter/receiver. table 1-2 lists pin names and numbers. generally, all unused input pins should be connected to ground and unused outputs should be left unconnected. however, if pins txovh_7 to txovh_0 or rxin_8 to rxin_0 are not used, they must be tied to a logic low level. some of the rxin pins may be used depending on the configuration. if pecl inputs, rxcki_hs, rxin_hs, or txcki_hs, are not used, they must be tied to +5 v power. figure 1-12. cn8223 pinout diagram vcc d[12] d[11] d[10] d[9] d[8] d[7] d[6] d[5] d[4] d[3] d[2] d[1] vcc gnd d[0] stat_int dl_int 8kcki oneseci oneseco ntest txout[8] txout[7] txout[6] tovh_clk vcc gnd tmrkr txovh[7] txovh[6] txovh[5] txovh[4] txovh[3] txovh[2] txovh[1] txovh[0] txout[5] txout[4] gnd 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 160 gnd locd rcv_hld fctrl_out[0] fctrl_out[1] fctrl_out[2] fctrl_out[3] fctrl_out[4] fctrl_out[5] fctrl_out[6] fctrl_out[7] fctrl_out[8] gnd vcc fctrl_out[9] fctrl_out[11] fctrl_out[12] fctrl_out[13] fctrl_out[14] fctrl_out[15] fctrl_out[16] fdat_out[0] fdat_out[1] fdat_out[2] gnd vcc fdat_out[3] fdat_out[4] fdat_out[5] fdat_out[6] fdat_out[7] fdat_out[8] rxin[7] rxin[8] rxovh[0] rxovh[1] rxovh[2] rxovh[3] vcc 119 120 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 vcc test3 reset test1 fctrl_in[7] fctrl_in[6] fctrl_in[5] fctrl_in[4] fctrl_in[3] fctrl_in[2] fctrl_in[1] fctrl_in[0] fdat_in[8] vcc fdat_in[7] fdat_in[6] fdat_in[5] fdat_in[4] fdat_in[3] fdat_in[2] fdat_in[1] fdat_in[0] prclk cs* w/r* as* gnd oe* a[7] a[6] a[5] a[4] a[3] a[2] a[1] d[15] d[14] d[13] gnd gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 at m transmitter/receiver cn8223 fctrl_out[10] 159 gnd rxovh[4] rxovh[5] rxovh[6] rxovh[7] rovh_clk[1] rovh_clk[0] rmrkr[1] rmrkr[0] rxcki rxcki_hs ? gnd vcc rxin[0] rxin[2] rxin[3] rxin_ hs ? rxin[5] txcki_hs ? txcki_hs+ rxin[6] tclko txin txout[0] txout[1] txout[2] txout[3] sel8bit txout_hs+ txout_hs ? vcc rxin[1] gnd vcc tclko_hs+ tclko_hs ? txcki rxcki_hs+ rxin[4] rxin_ hs+ 8223_012
1.0 product description cn8223 1.10 pin definitions atm transmitter/receiver with utopia interface 1-20 conexant 100046c table 1-2. hardware signal definitions (1 of 5) pin label signal name no. type i/o definition line framer/phy interface rxcki receive clock input 10 cmos/ttl i receive clock for all line rates except sts-3c, stm-1, and e4. rxcki_hs ? rxcki_hs+ receive clock input 11 12 pecl pecl i i differential pecl level for high-speed modes. receive clock for sts-3c, stm-1, and e4. tie to +5 v if not used. rxin_hs ? rxin_hs+ receive serial input 20 21 pecl pecl i i differential pecl level for high-speed modes. serial data in for sts-3c, stm-1, and e4. tie to +5 v if not used. rxin[0] rxin[1] rxin[2] rxin[3] rxin[4] rxin[5] rxin[6] rxin[7] rxin[8] receive input 15 16 17 18 19 22 25 154 155 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i i i i i i i i i receive parallel and taxi mode data inputs. tie to a logic low level if not used. txcki transmit clock input 30 cmos/ttl i transmit clock for all modes except sts-3c, stm-1, and e4. txcki_hs ? txcki_hs+ transmit clock input 23 24 pecl pecl i i differential pecl level for high-speed modes. transmit clock for sts-3c, stm-1, and e4. tie to +5 v if not used. txin transmit inputs 32 cmos/ttl i transmit serial data input for all modes except sts-3c, stm-1, and e4. tclko transmit clock output 31 cmos/ttl o transmit clock output for all modes except sts-3c, stm-1, and e4. txout[0] txout[1] txout[2] txout[3] txout[4] txout[5] txout[6] txout[7] txout[8] transmit output 33 34 35 36 42 43 56 57 58 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl o o o o o o o o o transmit parallel and taxi mode data outputs. tclko_hs+ tclko_hs ? transmit clock out 28 29 pecl pecl o o differential pecl level. transmit clock output for sts-3c, stm-1, and e4. txout_hs+ txout_hs ? transmit serial out 38 39 pecl pecl o o differential pecl level. transmit serial data output for sts-3c, stm-1, and e4. locd loss of cell delineation 122 cmos/ttl o asserted when cell synchronization is lost.
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.10 pin definitions 100046c conexant 1-21 framing overhead interface txovh[0] txovh[1] txovh[2] txovh[3] txovh[4] txovh[5] txovh[6] txovh[7] transmit overhead bus 44 45 46 47 48 49 50 51 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i i i i i i i i transmit bus input for sts-1/sts-3c/stm-1/g.832 overhead. tie to a logic low level if not used. rxovh[0] rxovh[1] rxovh[2] rxovh[3] rxovh[4] rxovh[5] rxovh[6] rxovh[7] receive overhead bus 156 157 158 159 2 3 4 5 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl o o o o o o o o receive bus output for sts-1/sts-3c/stm-1/g.832 overhead. rmrkr[1] rmrkr[0] receive overhead markers 8 9 cmos/ttl cmos/ttl o o used for overhead bus output. rmrkr[1] is an 8 khz output synchronized to the received plcp frame. rmrkr[1] is not available in ds-3 direct cell mapping mode. rovh_clk[1] rovh_clk[0] receive overhead clocks 6 7 cmos/ttl cmos/ttl o o used for overhead bus output. tovh_clk transmit overhead clock 55 cmos/ttl o used for bus input. tmrkr transmit overhead marker 52 cmos/ttl o used for bus input in modes 4, 5, 6 and 7 (oc3, oc1, e4 and g.832 e3). table 1-2. hardware signal definitions (2 of 5) pin label signal name no. type i/o definition
1.0 product description cn8223 1.10 pin definitions atm transmitter/receiver with utopia interface 1-22 conexant 100046c utopia/fifo interface fdat_in[0] fdat_in[1] fdat_in[2] fdat_in[3] fdat_in[4] fdat_in[5] fdat_in[6] fdat_in[7] fdat_in[8] fifo data bus 98 99 100 101 102 103 104 105 108 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i i i i i i i i i fifo interface input data bus for transmit. see section 2.7.1 . fctrl_in[0] fctrl_in[1] fctrl_in[2] fctrl_in[3] fctrl_in[4] fctrl_in[5] fctrl_in[6] fctrl_in[7] fifo control input 109 110 111 112 113 114 115 116 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i i i i i i i i fifo interface empty/full flag inputs. see section 2.7.1 . fdat_out[0] fdat_out[1] fdat_out[2] fdat_out[3] fdat_out[4] fdat_out[5] fdat_out[6] fdat_out[7] fdat_out[8] fifo data bus out 143 144 145 148 149 150 151 152 153 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl o o o o o o o o o fifo interface output data bus for receive. see section 2.7.1 . fctrl_out[0] fctrl_out[1] fctrl_out[2] fctrl_out[3] fctrl_out[4] fctrl_out[5] fctrl_out[6] fctrl_out[7] fctrl_out[8] fctrl_out[9] fctrl_out[10] fctrl_out[11] fctrl_out[12] fctrl_out[13] fctrl_out[14] fctrl_out[15] fctrl_out[16] fifo control outputs 124 125 126 127 128 129 130 131 132 135 136 137 138 139 140 141 142 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl o o o o o o o o o o o o o o o o o fifo interface strobe and control outputs. see section 2.7.1 . table 1-2. hardware signal definitions (3 of 5) pin label signal name no. type i/o definition
cn8223 1.0 product description atm transmitter/receiver with utopia interface 1.10 pin definitions 100046c conexant 1-23 microprocessor interface sel8bit 8/16 bit mode select 37 cmos/ttl i if asserted, this pin selects an 8-bit microprocessor bus. if not asserted, it selects a 16-bit bus. prclk processor clock 97 cmos/ttl i clock input to the microprocessor interface. all inputs are synchronous to this clock except oe~. all read and write operations require two cycles of prclk. prclk must run continuously at a minimum frequency of 2 times the cell rate. cs~ chip select 96 cmos/ttl i must be logic low to address chip. must be low to enable a read or write operation and should be stable throughout the cycle. as~ address strobe 94 cmos/ttl i if this pin is low, a new address is loaded on the rising edge of prclk for the operation in the following clock period. if this pin is high and cs~ is low, a read or a write operation is executed. the address strobe can stay low for multiple clock periods. address strobe cannot stay high with cs~ low for multiple clock periods. w/r~ write/read control 95 cmos/ttl i if this pin is low when cs~ is low, the following cycle is a read operation. if this signal is high when cs~ is low, the data presented at the end of the following clock cycle will be written if cs~ is still low on that cycle. oe~ output enable 92 cmos/ttl i this signal must be low to enable the data output for a read cycle. data bus outputs are three-stated if this signal is high. the data is valid between clock edges on a read cycle when this pin is low. this pin may be connected directly to ground, if desired. dl_int feac/hdlc interrupt 63 cmos/ttl o active-low data link channel interrupt output with open drain. stat_int status/counter interrupt 64 cmos/ttl o active-low status/counter interrupt with open drain. d[0] d[1] d[2] d[3] d[4] d[5] d[6] d[7] d[8] d[9] d[10] d[11] d[12] d[13] d[14] d[15] processor data bus 65 68 69 70 71 72 73 74 75 76 77 78 79 82 83 84 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o i/o this signal is a 16-bit bidirectional data bus for read and write data. table 1-2. hardware signal definitions (4 of 5) pin label signal name no. type i/o definition
1.0 product description cn8223 1.10 pin definitions atm transmitter/receiver with utopia interface 1-24 conexant 100046c microprocessor interface a[1] a[2] a[3] a[4] a[5] a[6] a[7] address bus 85 86 87 88 89 90 91 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl i i i i i i i seven-bit address input for addressing registers within the chip. addresses are loaded when as~ is low. clock and control 8kcki 8 khz reference clock input 62 cmos/ttl i used to synchronize plcp, and drive oneseco. oneseci one-second clock sync 61 cmos/ttl i 1 hz input used to latch line status every one second. rcv_hld receiver hold input 123 cmos/ttl i if asserted, this pin stops the cell receiver. ntest test input 59 cmos/ttl i connect to vcc for normal operation. test1 test3 test inputs 117 119 cmos/ttl cmos/ttl i i connect to ground for normal operation. reset reset 118 cmos/ttl i active-high pulse on power-up for at least 100 ns. this pin resets the internal state machines. it does not affect the contents of the registers, except bit 9 of register 0x02. oneseco one-second output 60 cmos/ttl o one-second count derived from count of 8 khz input. supply voltage vcc supply voltage 14 27 40 54 67 80 107 120 134 147 160 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl ? ? ? ? ? ? ? ? ? ? ? eleven pins are provided for supply voltage. gnd ground 1 13 26 41 53 66 81 93 106 121 133 146 cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl cmos/ttl ? ? ? ? ? ? ? ? ? ? ? ? twelve pins are provided for ground. table 1-2. hardware signal definitions (5 of 5) pin label signal name no. type i/o definition
100046c conexant 2-1 2 2.0 functional description this chapter describes the cn8223 architecture and functional blocks. figure 2-1 and figure 2-2 illustrates detailed signal paths of the receiver and transmitter. figure 2-1. cn8223 receiver block diagram sts-1/ sts-3c/ g.832 stm-1 serial/parallel ds-3/g.751 e3 framer sts-1/ sts-3c/ stm-1 g.832 framer serial bipolar data serial nrz data enable b3zs/hdb3 mux serial/ parallel external framer mode clock, sync, serial data octets mux parallel input octet, clock 100 mbps taxi interface phy mode plcp framer hec align. framer mux at m cell receiver alignment mode overhead output mux 8223_013 figure 2-2. cn8223 transmitter block diagram mux sts-1/ sts-3c/ stm-1 g.832 gen. overhead input plcp gen. at m cell gen. ds3/ g.751 e3 gen. b3zs/ hdb3 encode mux serial/ parallel data out 8223_014
2.0 functional description cn8223 2.1 microprocessor interface atm transmitter/receiver with utopia interface 2-2 conexant 100046c 2.1 microprocessor interface all control and status functions are provided via a direct microprocessor interface. address maps for the microprocessor are given in chapter 3.0 . there are two types of address spaces: read and write control registers read-only status registers and counters write operations are fully decoded. write operations to undefined addresses have no effect. read operations from undefined addresses have undefined results. the microprocessor interface to the cn8223 consists of 31 pins (detailed in table 1-2 ). the cn8223 connects to the microprocessor as if it were clocked ram memory. for timing diagram details, see section 4.3.1 . 2.1.1 8/16-bit interface the cn8223 supports an 8-bit or 16-bit microprocessor interface. to select the 8-bit data bus, connect the sel8bit pin to vcc. this configures all control and status registers in the part for byte-wide operation. byte addressing is accomplished by using the d15 pin as the byte high/low select. when d15 is low, the low byte of the addressed register is read or written, and the high byte is unaffected. when d15 is high, the high byte of the addressed register is read or written, and the low byte is unaffected. when reading register locations, the high byte of the addressed location is internally latched so that it can be read in the next operation. therefore, the low byte of a word address should be read first, then the high byte, to prevent loss of data. when sel8bit is low, the interface is configured with a 16-bit bus. 2.1.2 interrupts the cn8223 is designed for an interrupt-driven environment. after initialization, status events, error events, and counter overflows generate interrupts that run appropriate interrupt service routines. two active-low interrupt pins are provided for the microprocessor interface. stat_int provides interrupts for all status and error conditions. dl_int provides interrupts for the far end alarm control (feac) channel contained in the internal ds3 framer and for the internal high-level data link control (hdlc) formatter used for various data links. both interrupt pins are configured as open drain to facilitate external wire-or connections. each interrupt source has a bit in an interrupt enable register and in an interrupt status register. this allows the microprocessor to control which conditions cause interrupts and to determine the source of the interrupt. the status registers are described in chapter 3.0 . note: receiver interrupts will not function if the receive clock is not active. for example, if losing the signal to the line interface causes the receive clock recovery circuit to be disabled, the cn8223 will not respond to an los interrupt.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.2 line framers 100046c conexant 2-3 2.2 line framers this section describes the operation and control of the internal framers for ds3, e3 (both g.751 and g.832), e4 (g.832), sts-1, and sts-3c/stm-1 formatted serial streams. the transmit and receive serial interfaces can operate at up to 155 mhz. detailed timing information for the line interface is given in chapter 4.0 . the framer receive circuitry recovers the frame location from the serial stream and provides cell octets to the hec/plcp cell alignment block. all alarm and error conditions are monitored and reported in status registers and event counters. the framer transmit circuitry receives cell octets from the hec/plcp cell alignment block and adds line framing overhead information. all alarm and error conditions can be generated from control registers. external interfaces to this block and the interface to the rest of the cn8223 are illustrated in table 1-2 . the cn8223 line mode is set for both transmit and receive in the config_1 register [0x00]. table 2-1 lists the valid line modes set by config_1. table 2-1. valid config_1 line mode settings, bits 7?0 type of line input signal phy type unframed input disable b3zs/ hdb3 external framer enable parallel interface enable hec align ds1 0 0 0 1 0 0 or 1 ds1 (externally gapped 192 bits/frame) 0 1 0 1 0 0 e1 1 0 0 1 0 0 or 1 e1 (externally gapped ts0 and ts16) 1 1 0 1 0 0 ds3, internal framer 2 0 0 or 1 0 0 0 or 1 ds3, external framer 2 0 0 1 0 0 or 1 ds3, external framer (gapped 84/85 bits) 2 1 0 1 0 0 e3, internal g.751 format 3 0 0 or 1 0 0 0 e3, external g.751 format 3 0 0 1 0 0 e3, external g.751 format (gapped first 16 bits) 31 0100 e3, internal g.832 format 4 x 0 or 1 0 0 1 e4, internal g.832 format 5 x 1 0 0 1 sts-1, internal framer 6 x 0 or 1 0 0 1 sts-3c/stm-1, internal framer 7 x 1 0 0 1 parallel or taxi interface, 53 octet cells 0 x 0 1 1 1 note(s): x = don ? t care.
2.0 functional description cn8223 2.2 line framers atm transmitter/receiver with utopia interface 2-4 conexant 100046c 2.2.1 internally framed transmit line interface in internal framer mode, the transmitter provides positive and negative pulse indications and a transmit output clock to an external line interface unit (liu) (or output clock and nrz serial data if internal b3zs/hdb3 encoding is disabled) in response to a transmit input clock. table 2-2 gives the internal framing mode interface connections. the functional timing for the transmit line interface is similar for all internal framer modes. figure 2-3 illustrates the interface timing when the internal b3zs/hdb3 encoder is enabled. the tclko phase shown can be inverted with invert tx clock output [bit 7] of the config_3 register [0x02]. table 2-2. internal framer transmitter interface connections signal name connect to cn8223 pin transmit clock input (txcki) txcki transmit clock output (tclko) tclko transmit positive data (txpos) txout[1] transmit negative data (txneg) txout[2] figure 2-3. internal framer transmitter interface timing with line encoding tclko txpos txneg 8223_015
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.2 line framers 100046c conexant 2-5 2.2.1.1 high-speed pecl transmit interface for sts-3c, stm-1, or e4, the high-speed pecl interface is used. this mode is used in any case where an external liu/decoder is used (such as e4 and sts-3c/stm-1 cmi decoding). if the mode is set to e4 or sts-3c/stm-1 in config_1, then the outputs are taken from the ? hs ? versions of the output pins. the tclko (and tclko_hs) phase shown can be inverted with the invert tx clock output control bit. table 2-3 lists the interface connections for the internal framing mode without line encoding. figure 2-4 illustrates the interface timing when the internal b3zs/hdb3 encoder is disabled. table 2-3. internal framing unencoded transmitter connections (sts-3c, stm-1, e4) signal name connect to cn8223 pin transmit clock input (txcki) txcki_hs transmit data (txdato) txout_hs transmit clock output (tclko) tclko_hs figure 2-4. internal framer transmitter interface timing without line encoding tclko txdato 8223_016
2.0 functional description cn8223 2.2 line framers atm transmitter/receiver with utopia interface 2-6 conexant 100046c 2.2.2 internally framed receive line interface in internal framer mode, the receiver inputs are positive and negative pulse indications, and the receive clock (and nrz serial data if internal b3zs/hdb3 decoding is disabled) comes from an external liu. table 2-4 lists the interface connections for all of the internal framing modes. the functional timing for the receive line interface is similar for all internal framer modes. figure 2-5 illustrates the interface timing when the internal b3zs/hdb3 decoder is enabled. the rxpos and rxneg inputs are sampled on the falling edge of the rxcki clock input. data inputs can be sampled on the rising edge of the input clock by setting invert rx clock sampling [bit 8] in register config_3 [0x02]. table 2-4. internal framer receiver interface connections signal name connect to cn8223 pin receive clock input (rxcki) rxcki receive positive data (rxpos) rxin[1] receive negative data (rxneg) rxin[2] receive loss of signal (rxlos~~) rxin[4] figure 2-5. internal framer receiver interface timing rxcki rxpos rxneg 8223_017
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.2 line framers 100046c conexant 2-7 2.2.2.1 high-speed pecl receive interface sts-3c, stm-1 and e4 use the high-speed pecl interface. this mode is used in any case where an external liu/decoder is used (such as e4 and sts-3c/stm-1 cmi decoding). if the mode is set to e4 or sts-3c/stm-1 in config_1, then the inputs are taken from the ? hs ? versions of the input pins. rxdati input is sampled on the falling edge of rxcki. rxdati can be sampled on the rising edge of the input clock by setting the invert rx clock sampling bit. table 2-5 lists the connections for internal framer rx with the encoder disabled; figure 2-6 illustrates the timing with the coder disabled. 2.2.2.2 receiver framing operation five modes are provided for receiver framing operation: ds3, g.751 e3, g.832 e3/e4, sts-1, and sts-3c/stm-1. in ds3 mode, a parallel-search framing circuit recovers the subframe and m-frame alignments in the ds3 signal. framing is initiated by an out-of-frame condition as determined by the receiver frame bit-check circuitry. when 3 out of 16 consecutive subframing (f) bits are in error or when 2 out of 3 consecutive m-frames have m bit errors, an out-of-frame condition is declared. in g.751 e3 mode, a serial search for the 10-bit fas pattern (1111 0100 00) is conducted. when three consecutive correct patterns are found, the receiver is declared to be in frame. an out-of-frame condition is declared when four consecutive incorrect fas patterns are detected. in g.804 e3/e4 and sts-1/sts-3c/stm-1 modes, an octet alignment by the serial-to-parallel conversion circuit is found in conjunction with an octet search for the sonet a1/a2 framing pattern (which is the same pattern as, but not related to, the plcp a1/a2 bytes). when two consecutive good patterns are found, the receiver is declared to be in frame. an out-of-frame (oof) condition is declared when four consecutive incorrect a1/a2 patterns are detected. in sts-3c/stm-1 mode, an octet alignment by the serial-to-parallel conversion circuit is found in conjunction with an octet search for the third a1 and the first a2 octets. in sts-1 mode, if sts-1 stuffing option [bit 15] in config_1 [0x00] is set, then columns 30 and 59 in the payload envelope are stuff columns, and these octets will not be interpreted as atm cell octets. if this bit is not set, then all 86 columns of the spe will be interpreted as atm cell octets. table 2-5. connections for internal framer rx, encoder disabled (sts-3c, stm-1, e4) signal name connect to cn8223 pin receive clock input (rxcki) rxcki or rxcki_hs receive data (rxdati) rxin[0] or rxin_hs receive loss of signal (rxlos~) rxin[4] figure 2-6. timing for internal framer receiver, encoder disabled rxcki rxdati 8223_018
2.0 functional description cn8223 2.2 line framers atm transmitter/receiver with utopia interface 2-8 conexant 100046c 2.2.3 externally framed transmit line interface in external framer mode, the transmitter inputs are a clock and a synchronization signal that indicate the position of framing bits in the ds1, e1, ds3, or e3 framing signal. the transmit data stream output is a single serial output. the synchronization signal period can be any multiple of the frame period. functional timing for the transmit line interface is similar for all external framer modes. these interfaces are compatible with conexant framers bt8360 for ds1, bt8510 for e1, bt8370 for e1/t1, and bt8330b for ds3 and e3. interface connections for these serial, external framing modes are given in table 2-6 . figure 2-7 illustrates the transmit timing for the ds1 interface. txcki is 1.544 mhz. txsyi has a rising edge prior to the sampling of the frame bit. this signal does not have to be present at every frame; in particular, it can be a superframe synchronization signal with a period of 3 ms. txdato is the output signal; it transitions in response to the rising edge of txcki and can be sampled on the following falling edge. the framing bit position content in the output stream is undefined. table 2-6. serial external framer transmitter interface connection signal name connect to cn8223 pin transmit clock input (txcki) txcki transmit sync input (txsyi) txin transmit data output (txdato) txout[3] figure 2-7. ds1 interface transmit timing 78s2345678fs234567 channel 24 channel 1 txcki txsyi txdato 8223_019
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.2 line framers 100046c conexant 2-9 figure 2-8 illustrates the transmit timing for the e1 interface. txcki is 2.048 mhz. txsyi has a rising edge prior to the sampling of the first bit of time slot 0. this signal can be present every 2 ms. txdato is the output signal; it transitions in response to the rising edge of txcki, and can be sampled on the following falling edge. the content of time slot 0 and time slot 16 of the output is undefined. figure 2-8. e1 interface transmit timing time slot 31 txcki txsyi txdato 78s 23 4 5 6781 2 3 45 678 time slot 0 8223_020
2.0 functional description cn8223 2.2 line framers atm transmitter/receiver with utopia interface 2-10 conexant 100046c figure 2-9 illustrates the transmit timing for the ds3 interface. txcki has a frequency of 44.736 mhz. txsyi (active low) is sampled on falling clock transitions, and txdato changes on falling clock edges. txsyi has a rising edge after the sampling of the overhead bit (once every 85 bits). txdato is the output signal; it transitions in response to the falling edge of txcki, and can be sampled on the following falling edge. this timing is compatible with the conexant bt8330b ds3/e3 framer, using the txovh output of that circuit to synchronize the cn8223 input. the content of the frame bit position is undefined. figure 2-9. ds3 interface transmit timing information field txcki txsyi txdato x frame bit position information field 8223_021
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.2 line framers 100046c conexant 2-11 figure 2-10 illustrates the transmit timing for the e3 interface. txcki has a frequency of 34.368 mhz. txsyi has a rising edge after the sampling of the last bit of the frame alignment signal. txdato is the output signal; it transitions in response to the falling edge of txcki, and can be sampled on the following falling edge. this timing is compatible with the conexant bt8330b ds3/e3 framer using the txovh output. the frame alignment signal position is filled with the value 0xcccc. this value provides the four overhead bits (required by etsi prets 300 214) that follow the frame alignment signal defined by itu g.751. 2.2.4 externally framed receive line interface the cn8223 external receive line interface has three inputs: clock, data, and frame sync. frame sync can be a multiple of the frame period. table 2-7 lists the receiver connections for all external framing modes. the receive line inputs consist of the receive clock (rxcki), the receive sync input (rxsyi), and the receive data input (rxdati) when the external framer mode is selected. figure 2-10. e3 interface transmit timing frame alignment signal position txcki txsyi txdato x110 0 information field x x x x x x x x x 8223_022 table 2-7. external framing mode receiver connections signal name connect to cn8223 pin receive clock input (rxcki) rxcki receive sync input (rxsyi) rxin[3] receive data input (rxdati) rxin[0] receive loss of signal (rxlos~) rxin[4]
2.0 functional description cn8223 2.2 line framers atm transmitter/receiver with utopia interface 2-12 conexant 100046c the input timings are all similar: rxdati and rxsyi are sampled on the falling edge of the input clock; and the low-to-high transition of the sync signal occurs during the interval of the frame bit for ds1 and ds3, with the first bit of time slot 0 for e1, and the first bit of the frame-alignment signal for e3. for brevity, only the ds1 timing is illustrated ( figure 2-11 ). the timing on this interface is similar to the timing on the transmit interface. it is compatible with conexant framers. the data and sync inputs can be sampled on the rising edge of the input clock by setting invert rx clock sampling [bit 8] of config_3 [0x02]. in all framed, serial line formats, the content of the framing bit positions is ignored. rxsyi does not need to be present every frame; it can be applied at any submultiple of the frame rate (e.g., once every esf superframe for ds1). figure 2-11. receiver ds1 line interface timing channel 24 rxcki rxsyi rxdati 8 7 channel 1 6 5 4 3 2 s 7 6 5 4 3 2 s f 8 7 8223_023
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.3 overhead generation 100046c conexant 2-13 2.3 overhead generation the cn8223 automatically receives and generates line overhead. for additional flexibility, line overhead can be monitored and inserted for sts-3c, stm-1, and g.832 e3/e4 modes. 2.3.1 internal ds3 mode the transmitter circuitry automatically generates all f and m framing bits. the transmitter calculates the parity of each m-frame and inserts this data into bits p1 and p2 of the following m-frame. bits x1 and x2 contain 1s unless transmit alarm control [bit 6] of config_2 [0x01] is set. if this bit is set, bits x1 and x2 contain 0s. all c bit positions are generated automatically by the transmitter. overhead generation of ds3 values is summarized in table 2-8 . table 2-8. ds3 overhead values overhead bits cn8223 operation x1, x2 yellow alarm bits set from config_2, bit 6. p1, p2 calculates and inserts frame parity. no error insertion. m123 internally generated 010 pattern. no error insertion. f1234 internally generated 1001 pattern. no error insertion. c1 subframe 1 application id channel. internally generated as all 1s. c2 subframe 1 network requirement bit. internally generated as all 1s. c3 subframe 1 feac channel. internally generated under processor control. c123 subframe 2 unused. internally generated as all 1s. c123 subframe 3 path parity. same value inserted as p1, p2 in all 3 bits. no error insertion. c123 subframe 4 febe indication. internally generated as all 1s. if receiver detects a path parity, or m123 or f1234 error, then non-111 code is inserted for one frame. c123 subframe 5 terminal data link. data or all 1s from internal hdlc formatter when enabled. c123 subframes 6, 7 internally generated as all 1s.
2.0 functional description cn8223 2.3 overhead generation atm transmitter/receiver with utopia interface 2-14 conexant 100046c 2.3.2 internal g.832 e3/e4 modes all framing overhead is generated automatically and the bip octet is calculated and inserted in the em position. the bip field can be errored using the txfeac_errpat register [0x03] and bip error insert [bits 12 ? 10 of config_2 [0x01]. all undefined overhead octets are inserted externally as described in section 2.3.5 , and individual overhead octets can be disabled (set to all 0s) using overhead control [bits 3 ? 0] of config_2 [0x01]. internally generated octets are fa1, fa2, em, and ma. overhead generation of g.832 e3 and e4 values is summarized in table 2-9 . 2.3.3 internal g.751 e3 mode the fas pattern is automatically generated by the transmitter circuitry. the transmitter also inserts the a bit as determined from transmit alarm control [bit 6] of config_2 [0x01]. overhead generation of g.751 e3 values is summarized in table 2-10 . table 2-9. g.832 e3 and e4 overhead values overhead bits cn8223 operation fa1/fa2 inserts standard values (0xf6, 0x28) or can be inserted externally through port txovh[7:0]. if this bit is disabled, the value is 0x00. em calculates and inserts bip8. errors can be inserted using the txfeac_errpat register. allows single error insertion or all 0 value (continuous error). tr always inserted through port txovh[7:0]. ma calculates and inserts line febe based on incoming em errors. can be set for febe = all 1s or all 0s. inserts ferf and timing marker from register. can be disabled to all-0s or inserted from txovh[7:0]. nr always inserted through port txovh[7:0]. gc inserted externally through port txovh[7:0] or from internal hdlc formatter, if enabled. p1 e4 mode only. always inserted through port txovh[7:0]. p2 e4 mode only. always inserted through port txovh[7:0]. table 2-10. g.751 e3 overhead values overhead bits cn8223 operation fas 10-bit pattern internally generated ? 1111010000. no error insertion. a alarm bit set from config_2, bit 6. n data or all 1s from internal hdlc formatter when enabled.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.3 overhead generation 100046c conexant 2-15 2.3.4 sts-1 and sts-3c/stm-1 modes all framing overhead is generated automatically and all bip overhead is calculated and inserted in the proper positions. bip fields can be errored using the txfeac_errpat register [0x03] and bip error insert [bits 12 ? 10] of config_2 [0x01]. groups of overhead octets can be disabled (set to all 0s) using overhead control [bits 3 ? 0] of config_2. internally generated octets are a1, a2, c1, b1, b3, c2, h1, h2, h3, g1, b2, k2, h4, and m1. in sts-1 mode, if sts-1 stuffing option [bit 15] in config_1 [0x00] is set, then columns 30 and 59 in the payload envelope are stuffed with all 0s and are not available for atm cell octet transport (resulting in a total of 84 columns available for transport). if this bit is not set, then all 86 columns of the spe are available for atm cell octets. the c1 octet can be programmed to be obtained from the txovh bus by setting enable external section trace [bit 1] of config_4 [0x29]. the c1 values generated are listed in order of precedence in table 2-11 . the pointer value generated in sonet/sdh modes is controlled by stm-1/sts-3c pointer [bit 0] in the config_4 register [0x29]. this bit should be set low for sts-1 operation. when this bit is low, the h1/h2 pointer value is fixed at 0x620a. when this bit is set high (for stm-1 operation), the au-4 pointer value is fixed at 0x6a0a (ss bits = 10). overhead generation of sts-1, sts-3c, and stm-1 values is summarized in table 2-12 . table 2-11. c1 values mode control bit c1 octet value disable c1 config_2[0] 00 enable external config_4[1] from txovh bus sts-1 mode config_1[2:0] 01 sts-3c/stm-1 mode config_1[2:0] 01,02,03 table 2-12. sts-1, sts-3c, and stm-1 overhead values (1 of 2) overhead byte cn8223 operation a1, a2 inserts standard values (0xf6, 0x28) or may be inserted externally through port txovh[7:0]. if this bit is disabled, the value is 0x00. c1 internally generated (0x00 if disabled; 0x01 in sts-1 mode; 0x01, 0x02, and 0x03 in sts-3c mode). can be externally inserted through port txovh[7:0]. b1 calculates and inserts b1. errors can be inserted using the txfeac_errpat register. allows single error insertion or all-zero value (continuous error). e1 always inserted through port txovh[7:0]. f1 always inserted through port txovh[7:0]. d1 ? d3 inserted externally through port txovh[7:0] or from internal hdlc formatter, if enabled. h1, h2, h3 internally generated. the h1 values are 0x62 in sts-3c mode and 0x6a in stm-1 mode. the h2 value is 0x0a in both sts-3c and stm-1 modes. the h3 value is 0x00. if overhead insertion is disabled, all values are 0x00.
2.0 functional description cn8223 2.3 overhead generation atm transmitter/receiver with utopia interface 2-16 conexant 100046c h4 this byte is no longer used by the cn8223. its value is insignificant. h4 is the number of octets between the h4 octet position and the next cell starting position in the payload and thus has a value ranging from 0 to 52. its value will change in each frame because the payload does not hold an integral number of cells. this used to be the mechanism to locate cell boundaries but is no longer used since the hec alignment technique was developed. thus, the value in this position does not really matter. the cn8223 transmitter still generates this value but the receiver does not pay attention to it. b2 calculates and inserts b2. errors can be inserted using the txfeac_errpat register. allows single error insertion or all-zero value (continuous error). k1, k2 the k1 and k2 (ferf) values are internally generated through register 0x32. they can also be inserted externally through port txovh[7:0]. d4 ? d12 always inserted through port txovh[7:0]. z1 always inserted through port txovh[7:0]. m1 calculates and inserts line febe, based on incoming b2 errors. can be set for febe = all 1s or all 0s. e2 always inserted through port txovh[7:0]. j1 always inserted through port txovh[7:0]. b3 calculates and inserts b3. errors can be inserted using the txfeac_errpat register. allows single error insertion or all-zero value (continuous error). c2 three options: if disabled, value = 0x00 can be internally generated (0x13) can be externally inserted through port txovh[7:0] g1 calculates and inserts path febe (or all 1s or all 0s). inserts path rdi and qualifier (path yellow). if disabled, inserts value of 0x00. f2 always inserted through port txovh[7:0]. z3, z4 always inserted through port txovh[7:0]. z5 always inserted through port txovh[7:0]. table 2-12. sts-1, sts-3c, and stm-1 overhead values (2 of 2) overhead byte cn8223 operation
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.3 overhead generation 100046c conexant 2-17 2.3.5 transmit framing overhead interface an octet interface is available for external insertion of certain framing overhead in sts-1/sts-3c/stm-1 and g.832 e3/e4 framing modes. the interface consists of an output clock on tovh_clk, an output marker on tmrkr, and an 8-bit input bus for overhead octets. the timing for this interface is illustrated in figure 2-12 . there is a clock pulse on the tovh_clk output for each overhead octet that appears in the framing format and that is provided on the bus input. the bus input is sampled on the falling edge of the tovh_clk signal. tmrkr is high on a particular octet in each mode to synchronize external circuitry. all overhead octets can be provided by external insertion if enable external overhead [bit 15] in config_2 [0x01] is set. if this bit is not set, only octets that are not internally generated are obtained from the external interface. section 2.3.1 , section 2.3.2 , section 2.3.3 , and section 2.3.4 describe internally generated octets. in sts-1 mode, there are four clock pulses on tovh_clk for each row in the framing format (a total of 36 clock pulses per frame). the synchronous payload envelope (spe) starts immediately after the row 1 overhead (the j1 octet follows the c1 octet). tmrkr is high during row 1 of the framing format (octets a1, a2, c1, j1). sts-3c/stm-1 mode has the same format except there are 10 clock pulses for each row for a total of 90 clock pulses per frame. in sts-1/sts-3c/stm-1 modes, the content of octets d1, d2, and d3 is from the internal hdlc formatter, if enabled. these octets can also be provided via the txovh[7:0] input. in g.832 e3 mode, there is a total of 7 clock pulses per frame and tmrkr is high during the fa1 and fa2 octets. in g.832 e4 mode, there is a total of 16 clock pulses per frame, and tmrkr is again high during the fa1 and fa2 octets. the txovh[7:0] inputs should be connected to ground if all 0s octet data is desired for octets that are not internally generated. figure 2-12. transmit framing overhead interface timing tovh_clk tmrkr a1 a2 c1 j1 txovh[7:0] 8223_024
2.0 functional description cn8223 2.3 overhead generation atm transmitter/receiver with utopia interface 2-18 conexant 100046c 2.3.6 receive framing overhead interface an octet interface is available for external observation of all framing overhead in sts-1/sts-3c/stm-1 and g.832 e3/e4 framing modes. the interface consists of two output clocks on rovh_clk[1,0], two output markers on rmrkr[1,0], and an 8-bit output bus rxovh[7:0]. timing for this interface is illustrated in figure 2-13 . there is a clock pulse on the rovh_clk[1] output for each section and line overhead octet in sts-1 and sts-3c/stm-1 modes and for all overhead octets in g.832 e3 and e4 modes. there is a clock pulse on the rovh_clk[0] output for each path overhead octet in sts-1 and sts-3c/stm-1 modes. the rmrkr[1,0] outputs and the bus output are set up prior to the rising edge of the clocks and can be sampled externally on the rising edge of rovh_clk[1,0]. the rmrkr[1] output is high during row 1 overhead in all modes (a1, a2, and c1 in sts-1/sts-3c/stm-1 modes and fa1, fa2 in g.832 e3/e4 modes). the rmrkr[0] output is high during row 1 path overhead (octet j1) in sts-1 and sts-3c/stm-1 modes. there are two marker and clock outputs for sts-1 and sts-3c/stm-1 modes because the sonet frame and payload envelopes can be offset from each other. in sts-1/sts-3c/stm-1 modes, the contents of octets d1, d2, and d3 are provided to the internal hdlc receiver. the gc octets of the e3 and e4 formats are also provided to the hdlc receiver. terminal data link bits in ds3 mode (c bits of subframe 5) and the n-bit in g.751 e3 mode are also provided to the hdlc receiver. mode overhead octets output per frame sts-1 36 sts-3c/stm-1 90 g.832 e3 7 g.832 e4 16 figure 2-13. receive framing overhead interface timing rovh_clk[1] rmrkr[1] a1 a2 c1 rxovh[7:0] rovh_clk[0] rmrkr[0] 8223_025
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.4 status and alarms 100046c conexant 2-19 2.4 status and alarms the cn8223 automatically receives and generates alarms. 2.4.1 status and counter interrupts the status interrupt pin stat_int can be programmed to provide an interrupt on any occurrence in the line_status register [0x38]. each of these signals generates a receive status interrupt if the corresponding interrupt is enabled in the en_line_int register [0x2d]. to determine if an interrupt is caused by a phy status event, the line_status register is read. this clears the interrupts in that register. two types of interrupts are provided: error and alarm. error signals cause an interrupt on each occurrence of an error condition. error signals are bits 9 ? 13 in the line_status register. alarm signals provide an interrupt on change of state. all other indications in line_status are alarm indications. interrupt status bits for the line/phy counter overflows are located in the ovfl_status register [0x3a]. the enables for these interrupts are in en_ovfl_int [0x2f]. all counters are 16 bits. if a counter is set to interrupt, it rolls over to zero when it exceeds its maximum value. if a counter is not set to interrupt, it saturates at its maximum value of 65,535 and ignores further events. to determine if an interrupt has been caused by a counter, the microprocessor reads the ovfl_status register. if the interrupt for a particular counter is not set, the counter saturates at a value of 65,535 and stays at that value until read. if enable one-second latching of line counters [bit 13 in config_1 [0x00] is set, then at each one-second interval defined by the input oneseci, the current counter value is latched for the following one-second interval, and the counter is cleared. if the counter is again read in that one-second interval, the current value of the counter is read and then cleared. the lcv counter [0x40] is always latched (and the counter cleared) by the oneseci input regardless of the setting of enable one-second latching of line counters. when this counter is read, the latched value is presented and then cleared. subsequent reads prior to the next oneseci latching event produce a value of zero.
2.0 functional description cn8223 2.4 status and alarms atm transmitter/receiver with utopia interface 2-20 conexant 100046c 2.4.2 alarm signal generation three alarm signals can be generated by the transmitter in ds3 mode. these alarms are generated by setting transmit alarm control [bits 6 ? 4] of the config_2 register [0x01]. the yellow alarm is contained in the x1 and x2 bits. ds3 ais has the highest priority, followed by idle code, and finally yellow alarm. ds3 febe alarms are generated automatically in the transmitter when the receiver detects either a frame bit error or a c-parity error in an m-frame. when no alarm condition is present, the febe channel contains all-1s. when an alarm is to be sent (as determined by the receiver) the febe channel is set to all 0s for one m-frame for each error occurrence. in g.751 e3 mode, transmission of ais (unframed all 1s) is enabled by setting transmit alarm control [bit 4] high. transmission of yellow alarm is enabled by setting transmit alarm control [bit 6] high. this causes the transmitted a-bit to be set to one. in g.832 e3/e4 modes, transmission of ais or the ma ferf indication is enabled by setting transmit alarm control [bits 4 or 5], respectively. the ma timing marker bit can be set by setting transmit alarm control [bit 6]. in sts-1 and sts-3c/stm-1 modes, transmission of line alarm indication signal (ais), line far end receive failure (ferf), and various path indications can be enabled as described in section 3.3 .
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.4 status and alarms 100046c conexant 2-21 2.4.3 alarm detection the internal framers contain status indicators to obtain alarm information for link maintenance. table 2-13 shows the error indications by line mode. this table is repeated as table 3-17 , in chapter 3.0 . table 2-13. status indications for all modes (register 0x38) bit sts-1/sts-3c/ stm-1 internal ds3 g.832 e3/e4 internal g.751 e3 ext. framer (57 octet) 15 line febe error 0 0 0 0 14 one-second count one-second count one-second count one-second count one-second count 13 signal label mismatch invalid febe payload type mismatch invalid febe invalid febe 12 path ferf error febe all 1s ma ferf febe all 1s febe all 1s 11 path febe error plcp febe error ma febe plcp febe error plcp febe error 10 summary bip error plcp bip error em bip error plcp bip error plcp bip error 9 line ferf plcp frame error x plcp frame error plcp frame error 8 loc plcp yellow/loc loc plcp yellow plcp yellow 7 sts lof 2 ? 3 plcp lof 2 ? 3 e3/e4 lof 2 ? 3plcp lof 2 ? 3plcp lof 2 ? 3 6 sts lof plcp lof e3/e4 lof plcp lof plcp lof 5 sts oof plcp oof/loc e3/e4 oof plcp oof plcp oof 4 path yellow ds3 x-bit yellow x e3 a-bit yellow x 3 path ais ds3 idle code x x x 2 line ais ds3 ais e3/e4 ais e3 ais x 1 sts lop ds3 oof x e3 oof x 0 los (input) los (input) los (input) los (input) los (input) note(s): ? x ? means content should be disregarded.
2.0 functional description cn8223 2.5 parallel line interface atm transmitter/receiver with utopia interface 2-22 conexant 100046c 2.5 parallel line interface the cn8223 has a parallel line interface consisting of txout[8:0] and rxout[8:0]. these octet ports allow interfacing of external framers or other devices that use parallel data. table 2-1 , illustrates the architecture of this parallel interface. also, this interface can be used for the advanced micro devices taxi interface chipset. 2.5.1 taxi interface the parallel port of the cn8223 can be configured to interface directly with amd ? s taxi transmit/receive chipset. to enable this mode, set the following values in each of these registers: the transmit interface logic automatically generates the signals needed by the taxi transmitter to insert jk sync and tt start-of-cell symbols before each transmitted data cell of 53 octets. when no transmit port is active, the transmitter sends continuous jk sync symbols. the receiver interface logic detects the tt start-of-cell command and synchronizes its cell circuitry to receive and process the 53-octet cell data. the receiver ignores all incoming jk sync signals while awaiting the reception of the tt symbol. the receiver is not clocked on any command or data octet if the violation indication is present on rxin[8]. none of the indications in the line_status register [0x38] are valid in taxi mode except for one second count. any other indications should be ignored. violations will be counted in line counter 2. all cell status and cell event counters operate as in other modes. in taxi mode, the capability to shut down the output of cells to the fifo interface is lost because of the use of the rcv_hld pin. in this mode, the control bits in cell_val or external logic using the vltn signal must be employed for this function. note: source and line loopbacks are not functional in taxi mode due to the asymmetry between the transmit and receive control lines. config_1 (0x00): set the 8 lsbs to 0xe0. config_3 (0x02): set enable hec coset (bit 0) and invert rx clock (bit 8) high. config_4 (0x29): set enable taxi interface (bit 3) high.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.5 parallel line interface 100046c conexant 2-23 timing information for taxi mode is found in section 4.3.5 . pin connections for the taxi chipset and the cn8223 are listed in table 2-14 . 2.5.2 transmit parallel interface interface connections for the transmit parallel interface mode are listed in table 2-15 . txod and txdelo are mapped to txin and txout[8], respectively. figure 2-14 illustrates the transmit timing for the parallel interface. txcki has a frequency of up to 20 mhz. in parallel mode, the synchronization signal txod marks the octet clocks where the cn8223 does not provide a new data octet on the txdat output. this could be used for marking all of the overhead (non-atm payload) octets in a data stream. alternatively, txod can be held low and a gapped octet clock provided from the external circuitry to the cn8223 on txcki. txdat is the output signal; it transitions in response to the rising edge of txcki, and can be sampled on the following falling edge externally. txdelo also transitions in response to the rising edge and marks the first octet of each 53-octet cell. table 2-14. pin connections between taxi chipset and cn8223 signal name from taxi chipset connect to cn8223 pin receive clock (clk) rxcki receive data (do 7-0) rxin[7:0] receive command (co 1) txin receive command strobe (cstrb) rcv_hld receive violation (vltn) rxin[8] transmit clock (clk) txcki transmit data (di 7-0) txout[7:0] transmit command (ci 1) txout[8] transmit command (ci 0,2,3) gnd transmit strobe (strb) tclko table 2-15. transmit parallel interface mode connections signal name connect to cn8223 pin transmit clock input (txcki) txcki transmit octet disable (txod) txin transmit data output (txdat) txout[7:0] transmit cell delineation (txdelo) txout[8]
2.0 functional description cn8223 2.5 parallel line interface atm transmitter/receiver with utopia interface 2-24 conexant 100046c figure 2-14. transmit parallel interface timing txcki txdat[7:0] txod data data data txdelo 8223_026
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.5 parallel line interface 100046c conexant 2-25 2.5.3 receive parallel interface interface connections for the receive parallel interface mode are listed in table 2-16 . figure 2-15 illustrates the receive timing for the parallel interface. in parallel mode, data octets are provided on rxdat[7:0] with an octet clock (up to 20 mhz) on rxcki. the octet data is sampled on the falling edge of rxcki. the data inputs can be sampled on the rising edge of the input clock by setting invert rx clock sampling [bit 8] of config_3 [0x02]. an idle octet indicator can be provided on rxod as illustrated in figure 2-15 . the cn8223 ignores all octets for which the rxod input is high. this input can be used to mark framing overhead (non-atm payload) octets. table 2-16. receive parallel interface mode connections signal name connect to cn8223 pin receive clock input (rxcki) rxcki receive octet disable (rxod) rxin[8] receive data input (rxdat) rxin[7:0] figure 2-15. receive parallel interface timing rxcki rxdat[7:0] rxod data data (ignored) data data 8223_027
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-26 conexant 100046c 2.6 atm cell processing the atm cell processing block is located between the line framers and fifo port blocks of the cn8223 (see figure 1-3 ). this functional block interfaces between the octet data and cell data portions of the chip. the cn8223 supports cell delineation via either plcp or hec alignment for ds1, e1, ds3, e3, e4, sts-1, and sts-3c/stm-1 rates. at ds3 and e3 rates, all required stuffing functions are supported. 2.6.1 cell generation for transmit cell generation refers to the formatting of 53-octet atm cells from 48- or 52-octet payload data from the fifo interface for hand-off to the line framer transmitter. the cn8223 provides modes that generate complete cells as well as modes that pass entire 53- or 57-octet cells directly from the fifo interface. cell modes and other per-port controls are in the four cell_gen_x registers [0x04 ? 0x07]. the generation process operates autonomously with a handshake protocol through the fifo interface. cells are forwarded automatically to the line framer for transmission. when full atm cell generation is performed, a 5-octet header is generated by the cn8223. the vci and other fields in the first 4 octets come from microprocessor control registers. the hec in octet 5 is calculated and inserted by the cn8223. hec coverage over 4-header octets (atm) or 3-header octets (smds/802.6) is selectable by hec coverage [bit 1] of config_3 [0x02]. the remaining 48 octets are payload and are taken from the fifo interface. the cn8223 calculates and overwrites the crc field to complete the 53-octet cell. a cell-ready indication controls the cell generation process from the external atm interface circuit to the cell generation block. when the atm interface indicates that it has the first cell of a message ready, the cell generation block begins formatting a non-idle cell for transmission using the octet data and cell delineation control inputs at the interface. the cell generation circuitry automatically generates idle cells until the external fifo indicates that another cell is ready for transfer. the header and payload for idle cells are programmable via control registers. when the next cell is ready, the host presents the data and cell delineation control inputs.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.6 atm cell processing 100046c conexant 2-27 two rate control registers are provided for control of the port sources to allow programmable rate shaping of cell transmission. the ratio of active to idle cells is programmable with 0.4 % granularity. the cell generation process maintains status counts of non-idle cells transmitted for each of the four sources. table 2-17 lists the four cell generation modes provided by the cn8223. 2.6.1.1 cell_gen_x register per-port cell generation registers for fifo ports 0 ? 3 are in the four cell_gen_x registers [0x04 ? 0x07]. cell generation mode [bits 1,0] selects the operating mode for the generation circuit. the four modes described in table 2-17 are provided. in 52-, 53-, or 57-octet modes, the individual header fields obtained from the fifo interface can be overwritten. this overwriting is accomplished with the values found in the tx_hdr registers for a particular port by setting the appropriate field insertion control bit in the cell_gen_x register. in 48-octet mode the header fields always come from the programmed value in the corresponding tx_hdr register. the overhead fields of active cells are taken from the locations listed in table 2-18 or set to the indicated values. table 2-17. cell generation modes mode function 48-octet mode provides for full atm generation. forty-eight octets are taken from the fifo interface, the appropriate header fields are attached, and the payload crc is overwritten to form the atm cell. 52-octet mode allows a 53-octet cell, less the hec octet, to be transferred from the fifo interface. the hec is calculated and inserted by the cn8223. the payload crc for aal3/4 can be inserted, or checked and transferred without modification. both the hec and the payload crc can be optionally disabled or errored on a single-event basis. the cell generation process also provides hec coset generation, atm payload scrambling. in each of the above modes, any header field can be overwritten with information from control registers. 53-octet mode allows entire 53-octet cells to be transferred from the fifo interface. this is the mode used when port 0 is configured for utopia. 57-octet mode allows the input of entire 57-octet plcp slots from the fifo interface. can be used for external plcp insertion or test generation purposes.
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-28 conexant 100046c disable hec [bit 9] and disable payload crc [bit 10] in the cell_gen_x registers [0x04 ? 0x07], disable the field generation and allow the existing field to pass. error hec [bit 11] and error payload crc [bit 12] force a single error occurrence in the generated field. the error functions are cleared after the error is generated. this allows the microprocessor to easily generate a specific number of errors. the error pattern programmed in the txfeac_errpat register [0x03] is used with the error hec control to generate a specific number of hec errors for checking receiver error correction/detection circuitry. the error payload crc bit inserts 4-bit errors into the payload crc field. the inhibit single cell generation [bit 13] field in cell_gen_x, inhibits cell transmission from the port for a single cell interval. a single idle cell (with header contents as defined in the transmit idle header register [0x0a ? 0x0b] and payload set to all 0s) is transmitted in place of a data cell from this port at the next cell interval if the priority control tries to obtain a cell from this port. this bit is cleared by the cell generation circuitry after the idle cell has been transmitted or if a cell from another port is selected by the priority control. the microprocessor can poll this bit to determine when the idle cell insertion has been completed. idle cells are automatically generated when no transmit port is active. the header for idle cells is obtained from the tx_idle_xx registers, and the hec is automatically calculated. the payload for idle cells is obtained from the idle_pay register [0x2a]. this data octet is inserted in all octet positions of the idle cell payload. the crc-10 can be inserted if required by setting disable payload crc of cell_gen_x to zero. 2.6.1.2 cell generation status and status interrupts for transmit a per-port count of cells transmitted is maintained in the cell_sent_cntx counters [0x4e ? 0x51] for each port. these counters can be programmed to cause an interrupt in the cell_status register [0x3b] by setting enable bits in the en_cell_int register 0x30]. the interrupt clears when cell_status is read. if the counter interrupt is not enabled, the counter stops at its maximum value of 65,535. if the interrupt is enabled, the counter interrupts on ? roll over ? and continues counting. the counter clears when it is read. table 2-18. overhead field locations overhead field source cell header header register tx_hdr or fifo input header error control hec generation circuit or fifo input segment type fifo input sequence count fifo input length field fifo input payload crc payload crc generation circuit or fifo input
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.6 atm cell processing 100046c conexant 2-29 2.6.2 cell validation for receive cell validation refers to the checking of cells coming in from the phy block for proper format. modes that deliver 48-, 52- or 53-octet cells, or 57-octet plcp slots to the fifo output ports are provided by the cn8223. four modes are available for cell output: a test mode writes the entire 57-octet plcp slot to the fifo interface. a 53-octet mode writes the 53-octet atm cell to the fifo interface. a 52-octet mode writes the atm cell without the hec octet to the fifo interface. a final mode delivers 48-octet cell payloads to the fifo interface. when the utopia interface mode is used, only 53-octet output is available. the protocol verification provided includes hec validation with atm or smds/802.6 coverage, cell header filter/screen against four maskable 32-bit programmable values, validation of payload length per segment type, and correct payload crc value. status reporting on validation steps is via error counters and status register indications. status bits can be programmed to generate interrupts to the microprocessor. each validation step can be individually disabled. cells are routed to one of four output ports if a match to that port ? s programmable header value is made. each cell is output to the atm interface after a 6- or 10-octet buffer to allow for header processing. a ? cell-valid ? output pin is provided to indicate that none of the enabled error checks detected an error. the utopia internal fifo or external circuitry is notified to discard the cell when the valid indication goes inactive. idle cells are automatically deleted from the atm layer output. parity and control/delineation signals are provided with each octet at the port interface. the microprocessor receives status and error counts as cell validation proceeds. all event and error counters can be programmed to cause an interrupt on overflow. reading the interrupt source register allows the microprocessor to identify overflows and update internal counts. all counters can be read by the microprocessor and are cleared when read.
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-30 conexant 100046c 2.6.2.1 hec alignment in 53-octet mode, either the internal framer or the parallel input provides octet alignment information to the hec alignment state machine. each octet position is then searched for correct hec alignment to determine cell delineation. the hec alignment framing state machine is given in itu i.432. three states are present: hunt, pre-sync, and sync. the hunt state is entered when seven consecutive errored hec patterns are found at the current alignment location. the pre-sync state is entered when a candidate position contains the correct hec pattern. the sync state is entered when six consecutive, correct hec patterns at the candidate location are found. the hec state machine can be altered to include state integration by setting the integrate hec framing control bit in config_5. when this bit is set, the state machine has two additional states: ocd anomaly and verification. the ocd anomaly state is entered when seven consecutive errored hec patterns are found at the current alignment location. ocd anomaly status is indicated in bit 10 of config_5. after an integration time of x ms in the ocd anomaly state, the lcd defect state is entered. the lcd defect state is indicated in bit 8 of line_status [0x38] and on the locd output pin. the verification state is entered when six consecutive, correct hec patterns at the candidate location are found. after x ms in the verification state, the sync state is entered. the value of x is 4 ms for sonet/sdh modes and 2.5 ms for ds3 mode. this integration time is counted from the 8 khz reference input on the 8kcki input pin. a rising edge must be present on this input every 125 s for proper integration in this state machine. 2.6.2.2 cell_val control register cell validation refers to the error checking of received cells prior to output to the fifo interface. it is controlled via the cell_val register [0x14]. per-port output mode selects 48-, 52-, 53-, or 57-octet modes for each of the four ports. enable hec correction [bit 8] enables the hec correction mode for single-bit header errors. if this bit is set to zero, then no correction is performed, but error detection is always performed. error correction must be disabled if hec coverage [bit 1] in config_3 [0x03] is set for smds/802.6 mode, or if enable hec coset [bit 0] in config_3 is not enabled. header only output [bit 12] in cell_val enables a 5-octet output mode on port 3. only the 4 header octets of cells addressed to port 3 and the status octet in table 2-19 are output to the fifo port. in 53-octet cell formats, if status output is enabled with header only output, none of the other ports should be programmed for 53-octet output. enable status octet [bit 13] in cell_val sends a status octet to fifo port 3. it should only be used in 53-octet output mode. when this bit is set, the hec octet position in the fifo output data is omitted, and a status word as shown in table 2-19 is appended to the end of the cell as octet number 53. in 53-octet cell formats, if status output is enabled with the enable status octet bit, none of the other ports should be programmed for 53-octet output. the status word contains indications of port 3 header and payload errors as well as vci/vpi match information for the other three ports for each cell received. the status word bits are set only if the corresponding failure occurs and the check for that failure is enabled. the user data bit is derived from the pt field in the header as shown in table 2-20 and can be used as an aal5 eom marker. these two port 3 output options are available only if none of the ports are set to 57-octet output mode.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.6 atm cell processing 100046c conexant 2-31 if disable cell receiver [bit 14] of cell_val and disable port reception ? port x [bits 7 ? 4] of config_4 [0x29] are not set, then enabled checks are made on each cell received in the following sequence: 1. the hec is checked for errors under control of the hec coverage [bit 1] of config_3 [0x03]. correctable errors are corrected if enable hec correction [bit 8] of cell_val is set. the correction/detection state machine is implemented as defined in the atm uni/nni specifications. errors counted in either the cor_hec_err counter [0x49] or uncor_hec_err counter [0x4a] are also indicated in the corresponding bits in the event_status register [0x39]. hec error correction/detection is performed independent of any header screening that is enabled. error correction should be enabled only if hec coverage is 0 and enable hec coset [bit 0] of config_3 is 1. 2. the payload crc-10 is checked. errors are counted in the pay_crc_err counter [0x48] and indicated in event_status. no crc checking is performed on cells matching the idle header description. 3. the payload length is checked to be consistent with the segment type. table 2-19. status octet definition bit definition 0 hec error corrected for port 3 1 hec error not-corrected for port 3 2 payload length error for port 3 (aal3/4) 3 payload crc-10 error for port 3 (aal3/4) 4 user data bit for port 3 (aal5 eom) 5 header match port 0 6 header match port 1 7 header match port 2 table 2-20. pt header field and user data bit pt header field user data bit 0 0 0 0 0 0 1 1 0 1 0 0 0 1 1 1 1 0 0 0 1 0 1 0 1 1 0 0 1 1 1 0
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-32 conexant 100046c . errors are counted in the pay_len_err counter [0x4c] and indicated in event_status. no payload length checking is performed on cells matching the idle header description. all errors disabled by the global disables in cell_val are counted, and the first enabled error in the above sequence of checks is counted in the appropriate cell error counter. disabled errors will not cause the cell to be marked as invalid. header octets are compared to the hdr_val registers under control of the hdr_msk bits. this determines routing to the proper output port. if no match is made to any of the vci/vpi fields for the four ports or to the idle definition, the cell is counted in the non_match_cnt counter [0x57]. payload crc-10 and length checks can also be disabled on a per port basis by using the control bits in config_4. these bits simply disable the error from marking the cell as invalid and do not affect the counting of errors in any way. this feature can be used to route aal 3/4 cells to one port with checks enabled and aal5 cells to a different port with checks disabled. hec coverage [bit 1] in config_3 determines the calculation range for the hec. if this bit is low, the hec is calculated over header octets 1 ? 4 for atm cells. if this bit is high, the hec is calculated over header octets 2 ? 4 for smds/802.6 cells. validation checks can be individually disabled with the remaining control bits in the cell_val register [0x14]. disable hec check [bit 9] disables the check of the header error control octet. disable payload length check [bit 10] disables the check for consistency between the segment type field and the length field. disable payload crc check [bit 11] disables the check of the payload crc. the above disables are global disables for all ports and override the per-port control in config_4, which also contains per port disables for payload length and payload crc checks. 2.6.2.3 interrupts and status counters for cell validation cell error events are indicated with bits 0 ? 6 of the event_status register [0x39] and can cause an interrupt if enabled with the corresponding bit in the en_event_int register [0x2e]. status bits are latched at the event occurrence and are cleared when event_status is read. the error events are also counted, and interrupts on error counter overflows can be enabled in en_ovfl_int [0x2f]. counter overflow status is provided in ovfl_status [0x3a], and the status bits are cleared when the status register is read. these counters are not latched, and each counter is cleared individually when it is read. cell_rcv_cntx [0x52 ? 0x55] provides a count of all cells that are accepted for processing and delivery to port x. this count is based on a header match with the header value and mask bits that are set in the associated registers for port x. this count does not include cells discarded due to an error in the hec. idle_cell_cnt [0x56] is a count of valid cells received that match the programmed idle value and mask. non_match_cnt [0x57] is a count of active cells that did not match any of the programmed vci/vpi values (port or idle). segment type payload length bom or com 44 eom 4 ? 44 mod 4 ssm 8 ? 44 mod 4
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.6 atm cell processing 100046c conexant 2-33 counter overflow interrupts can be individually enabled. if a counter is set to interrupt, it rolls over to zero, sets the interrupt, and continues counting errors after it reaches its maximum value. if a counter is not set to interrupt, it saturates and holds when it reaches its maximum value (0xfff). the interrupt enable bits for the counters are found in the en_cell_int register [0x30], with the corresponding interrupt status in the cell_status register [0x38]. if one of the cell counter overflow interrupts occurs, the cell_status register can be read to determine which counter or counters overflowed. these interrupts are cleared when cell_status is read. some interrupts in the cell_status register are related to the transmission/reception of individual cells. these interrupts may be enabled in en_cell_int with corresponding status bits in cell_status. cell rcvd ? port x indicates the validation process has received a complete atm cell destined for port x. cell sent ? port x indicates a cell has been transmitted from source x. these interrupts are cleared when cell_status is read. 2.6.3 plcp cell generation for transmit in 57-octet plcp formats, the plcp overhead generation consists of the framing octets a1 and a2, the path overhead identifier (poi) octets, and the path overhead octets. all of these are generated by the phy transmit circuitry, but can be selectively disabled if desired. the a1 and a2 octets are generated according to tr-tsv-000773. the poi octets are determined by the particular plcp that is selected, but in each case they consist of a slot count and a parity bit. the ds3 plcp has 12 slots per frame, the ds1 and e1 plcp have 10, and the e3 plcp has 9. in each case, the poi octets provide a backwards count of the plcp slots in the frame, along with a parity bit. generation of the a1, a2, and poi octets can be disabled via the overhead control [bits 3 ? 0] of config_2 [0x01]. all path overhead growth octets zn and the path user channel f1 are forced to zero. the b1 octet is populated with a bip-8 code that is calculated over each plcp frame. the bip error insert [bits 12 ? 10] of config_2 control insertion of bip-8 errors in the generated plcp. if errors are to be inserted, a non-zero value written to the txfeac_errpat register inverts the corresponding bits of the b1 octet from that calculated by the bip-8 circuit in the following plcp frame. insert control bits are cleared after each frame when the errors are inserted. the register can be read to determine if this has occurred, so that the microprocessor can insert bip-8 errors as desired in each plcp frame.
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-34 conexant 100046c this capability can be used to verify far-end febe operation. bip generation can be disabled via the overhead control bits. the fields of the g1 octet are under control of the all 0s febe [bit 14], all 1s febe [bit 13], and transmit alarm control [bits 9 ? 4] of config_2. the febe controls operate as shown in table 2-21 . the yellow alarm bit in the g1 octet is set to the value contained in transmit alarm control [bit 7]. the c1 octet is under control of phy type [bits 2 ? 0] of config_1 [0x00], force cycle stuffing [bit 6] of config_3 [0x02], and overhead control [bits 3 ? 0] of config_2 [0x01] as shown in table 2-22 . the trailer content (except in e1 mode where there is no trailer) has each nibble set to 1100 unless overhead control [bit 0] is set. in this case, each nibble has the value 0000. in 53-octet formats, no plcp overhead is associated with each atm cell. the only overhead present is that contained in the line framing format, as discussed in section 2.2 . table 2-21. febe controls all 1s febe all 0s febe febe field value 0 0 bip-8 errors received 0 1 0000 1 0 1111 1 1 0000 table 2-22. c1 octet disable c1 generation phy type force cycle stuffing c1 octet value 1xx 00 0ds1, e1x 00 0 ds3, e3 0 per selected 8 khz reference (via config_1, bit 11) 0 ds3, e3 1 per default cycle
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.6 atm cell processing 100046c conexant 2-35 2.6.4 plcp cell validation for receive in 57-octet plcp formats, the phy receiver implements framing state machines for cell alignment as described in tr-tsv-000773. in 53-octet formats, the phy receiver implements the hec alignment state machine as described in itu i.432. in serial framed 57-octet mode, the phy receiver processes a serial stream to find plcp framing. octet synchronization is provided externally in ds1 and e1 modes. internal or external e3 octet synchronization and ds3 nibble synchronization are provided to the phy framer. physical layer framing patterns are automatically removed before recovery of the octet data. if unframed mode is enabled, the receiver will search each bit position to determine octet alignment. the 57-octet plcp framing state machine contains three states: in-frame, out-of-frame, and loss-of-frame. valid framing is found when two consecutive valid path overhead octets in sequence are observed after the a1, a2 framing octets. the out-of-frame state is entered only from the in-frame state, when there are errors in both the a1 and a2 octets or when there are two consecutive pn errors. this event is an oof event, and is counted. the lof state is entered after eight consecutive plcp frames in the out-of-frame state. stuffing and destuffing are provided according to the phy type setting in 57-octet formats. cycle stuffing is used at the transmit plcp for ds3 and e3 whenever the receive plcp is in the lof state or the rcv_hld input is high, and this function is enabled with receiver hold enable [bit 10] of config_1 [0x00]. cycle stuffing can also be forced by setting force cycle stuffing [bit 6] of config_3 [0x02] high. note: when the framing mode is dynamically modified between direct mapping and plcp framing, the cn8223 will go into an oof state. dynamic switching should only be used if necessary. 2.6.4.1 plcp status errors in either the a1 or a2 plcp framing octets cause an indication in the line_status register plcp frame error bit and are counted. plcp oof events are indicated by the plcp oof bit and counted. plcp lof events (oof for eight consecutive plcp frames) are indicated by the plcp lof bit. if an lof condition persists for more than 2 ? 3 seconds, the plcp lof 2 ? 3 status bit is set. this is determined by lof being set for three consecutive rising edges of the oneseci input. loss of cell delineation in 53-octet modes is indicated by the loc bit and counted. plcp oof and loc indications also appear on the locd output pin. the plcp yellow alarm status bit is set high after 10 consecutive frames with a plcp yellow alarm value of one and cleared after 10 consecutive frames of a value of zero. errors detected in the receiver bip-8 code checking circuit cause bip-8 error to be set and counted. febe error is set if any valid non-zero febe value (values of 1 through 8) is received. this condition is also counted in the rem_bip counter. invalid febe is set if any invalid febe value (9 through f) is received; a value of f also causes febe all 1s to be set. this value is used to indicate that the febe calculation is not supported at the far end of the circuit.
2.0 functional description cn8223 2.6 atm cell processing atm transmitter/receiver with utopia interface 2-36 conexant 100046c each rising edge at the oneseci input causes an indication in the one-second count bit. this indication can be used as a timing interrupt to coordinate status collection. if enable one-second latching of line status is set, the oneseci input also causes status indications in line_status to be latched. if an alarm condition is present during a one-second interval, it is available to be read on the successive interval. otherwise, the status is latched and held until it is read. if this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears the status register. enable one-second latching of line counters provides the same functionality for the counters. each of the line_status bits is latched until read and then cleared if the condition is no longer present. if a status condition clears before the register is read, the status bit is still held. current status can be obtained by reading the register twice in succession. 2.6.5 plcp transmit/receive synchronization for 57-octet formats, the plcp block must transmit segments at the same rate as they are received. for ds1 and e1, long-term synchronization of the bit clock rates establish this. for ds3 and e3 rates, the payload data rate is independent of the line rate, and a separate timing/synchronization mechanism is required. the ds3 and e3 plcps both have a 125 s frame period. the reference clock for this frame is taken from the received signal, or alternatively from an external reference supplied to the 8 khz clock input 8kcki. in either case, the transmit circuit generates one plcp frame per reference frame. in 53-octet formats, all frame structures are based on a 125 s period; consequently, no stuffing is required to synchronize the transmit and receive segments. clock and control inputs consist of the following: an external 8 khz reference for the plcp at e3 and ds3 a one-second input to synchronize status collection timing in multiple-port applications a ? hold receiver ? input that can externally disable cell validation when an external framer loses frame or signal three test inputs a reset input a one-second clock output is provided to allow synchronization of status collection for multiple cn8223s or for cn8223s and framers. when a single cn8223 is used, oneseco should be connected to oneseci. this timing output is derived from the external 8 khz reference clock input on 8kcki.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.7 fifo port/utopia interface 100046c conexant 2-37 2.7 fifo port/utopia interface the cn8223 has four bidirectional fifo ports used to interface to the atm layer outside the chip. these four ports share fdat_in and fdat_out 8-bit ports. each port has its own set of six control signals used for flow control and timing. (refer to figure 1-4 , for a diagram of the fifo port/utopia interface.) port 0 can be configured as a level 1 compliant utopia port for connection to other utopia components. when utopia mode is enabled, ports 1, 2, and 3 are unused. the utopia interface is detailed in section 2.7.5 . 2.7.1 fifo interface inputs and outputs the four-port fifo interface allows the connection of the cn8223 directly to dual-port rams, fifo rams, and other similar circuits. the fifo interface pins and their functions used for connection are listed in table 2-23 . transmit fifo port timing for the 53-octet mode is shown in figure 2-16 . detailed descriptions of the transmit fifo pin functions are given in table 2-24 . receive fifo port timing for the 53-octet mode is shown in figure 2-17 . detailed descriptions of the receive fifo pin functions are given in table 2-25 . table 2-23. fifo interface pin connections (1 of 2) cn8223 function fdat_in[8:0] transmit data with parity fctrl_in[0] port 0 transmit data fifo empty fctrl_in[1] port 1 transmit data fifo empty fctrl_in[2] port 2 transmit data fifo empty fctrl_in[3] port 3 transmit data fifo empty fctrl_in[4] port 0 receive data fifo full fctrl_in[5] port 1 receive data fifo full fctrl_in[6] port 2 receive data fifo full fctrl_in[7] port 3 receive data fifo full fdat_out[8:0] receive data with parity fctrl_out[0] port 0 receive data write strobe fctrl_out[1] port 1 receive data write strobe fctrl_out[2] port 2 receive data write strobe fctrl_out[3] port 3 receive data write strobe fctrl_out[4] port 0 receive cell invalid indication fctrl_out[5] port 1 receive cell invalid indication fctrl_out[6] port 2 receive cell invalid indication
2.0 functional description cn8223 2.7 fifo port/utopia interface atm transmitter/receiver with utopia interface 2-38 conexant 100046c fctrl_out[7] port 3 receive cell invalid indication fctrl_out[8] ports 0, 1, 2 receive cell sync marker fctrl_out[9] port 3 receive cell sync marker fctrl_out[10] receive fifo write error or receive start of cell fctrl_out[11] transmit cell sync marker fctrl_out[12] (1) port 0 transmit data read strobe fctrl_out[13] (1) port 1 transmit data read strobe fctrl_out[14] (1) port 2 transmit data read strobe fctrl_out[15] (1) port 3 transmit data read strobe fctrl_out[16] transmit plcp frame sync marker or transmit start of cell note(s): (1) fifo read strobes are forced inactive (high) during hardware or software resets. table 2-23. fifo interface pin connections (2 of 2) cn8223 function figure 2-16. transmit fifo port interface timing, 53-octet mode port x transmit 56 56 5 4 data read strobe transmit cell sync marker transmit start- of-cell marker transmit frame sync marker transmit data port x transmit data fifo empty octet 8223_028
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.7 fifo port/utopia interface 100046c conexant 2-39 table 2-24. fifo transmit pin functional descriptions cn8223 fifo pin function functional description transmit data fifo empty in the transmit direction, the transmit data fifo empty input inhibits the transmit data read strobe for a particular port. the empty flag from the fifo, when inactive, indicates that the fifo contains at least one entire cell of the appropriate length for the selected mode. data read strobes to a particular port are inhibited if the empty flag for that port is low. there are four of these signals, asserted low, one per port. transmit plcp frame sync if using fifo mode and plcp mapping, when 57-octet input is selected on the transmitter, the transmit plcp frame sync marker (fctrl_out[16]) is high during the first slot of the plcp frame to indicate the start of the frame. transmit start of cell marker in 53-octet mode, fctrl_out[16] indicates the transmit start of cell, informing the fifo that the next strobe will read the first octet of the cell to be transmitted. transmit cell sync marker the transmit cell sync marker is an additional output to delineate cell boundaries to the transmit data fifo. this marker is low during the read strobe requesting the last octet of a cell, and high during all other read strobes regardless of the programmed length of the cell to be transferred from the fifo. figure 2-17. receive fifo port interface timing, 53-octet mode port x receive 56 56 55 1234 data write strobe receive cell sync marker receive start- of-cell marker receive cell invalid indication receive data octet 8223_029 0 0
2.0 functional description cn8223 2.7 fifo port/utopia interface atm transmitter/receiver with utopia interface 2-40 conexant 100046c 2.7.2 transmit port priority mechanism each of the four transmit data read ports has a priority level that is programmable to four levels. the control bits for setting the port priority level are in the cell_gen_x control registers. priority level 0 is the highest priority, priority level 3 is the lowest (see table 2-26 ). if more than one port is assigned the same priority level, then arbitration occurs in port order with bandwidth allocated cyclically to port 0, port 1, port 2, and port 3. the priority state machine looks at the port empty flag inputs for all ports at priority level 0 and reads cells from these ports cyclically until all port flags indicate empty. if no cells are available at priority 0, the state machine then looks at the port empty flags for all ports at priority level 1 and reads cells from these ports cyclically as long as no priority 0 port has a cell ready. table 2-25. fifo receive pin descriptions cn8223 fifo input functional description receive data write strobe the receive data fifo interface strobes data octets from fdat_out[8:0] into an external fifo device on each rising edge of receive data write strobe. this strobe is a gated clock with 48-, 52-, 53-, or 57- strobes for the corresponding number of cell octets, depending on mode. there are four receive data write strobes, one per port. receive data fifo full this flag is active low. if receive data fifo full is asserted by the external fifo and the cn8223 attempts a write to that port data, loss occurs. if this happens, receive fifo write error pin (fctrl_out[10]) is asserted low. there are four receive data fifo full signals, one per port. receive cell sync marker the sync marker will be low during the last octet of data transfer and high during all other octets of the data transfer for each cell regardless of the number of octets selected for output. receive cell invalid indication this per-port signal indicates that a hec or other check has failed. the invalid indication will be low during the first octet of data transfer. if any enabled check fails, the invalid indication will be high during the last five octets of the cell. if no failures occur, the indication will stay de-asserted through the end of the cell. the fifo or a microprocessor must mark this cell as bad to prevent further processing. optional start of cell mode if start-of-cell/write error output [bit 15] in the cell_val register [0x14] is set, then fctrl_out[10] becomes an active-high start-of-cell output marker for the receiver, and fctrl_out[16] becomes an active-high start-of-cell output marker for the transmitter. these indicators are valid only in 53-octet input/output mode. in this mode, the receive fifo write error function is not available. table 2-26. priority levels cell_gen 3 cell_gen 2 priority level 00 0 01 1 10 2 11 3
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.7 fifo port/utopia interface 100046c conexant 2-41 if a higher priority port indicates that it has a cell ready during servicing of a lower priority port, service switches to the higher priority port after completion of the cell currently being formatted and transmitted. servicing of ports and priority levels continues in this manner until the lowest priority ports are serviced and empty. port priority programming is not intended to be dynamic and should be used only as a configuration setup. changes in port priority cannot take place until ports are inactive (via fifo empty flag or transmit rate shaping). unused ports should be programmed to the lowest priority level, and their empty flag inputs should be connected to ground. 2.7.3 transmit rate shaping control each of the four transmit data ports has a rate shaping control to allow the allocation of programmable bandwidth to cells originating from this port. the tx_rate_01 [0x09] and tx_rate_23 [0x08] registers control this function. the transmit circuitry contains a mod-256 master counter to control rate shaping. this counter is incremented for every atm cell that is transmitted, and it rolls over to 0 when count 255 is reached. the programmed rate value for a port in the tx_rate_xx registers determines the count range for which transmission from that port is allowed. for instance, if port 0 is programmed with a rate value of 63, transmission of cells queued at port 0 will be allowed for 64 (one more than the programmed value) of the 256 counts of the master counter. the transmission is spread over all counts of the counter so that transmission is not bursty. this gives port 0 a bandwidth allocation of 25 % of the total outgoing bandwidth even if all of the other ports are inactive. this allocation scheme is valid for rate values from 1 to 255 resulting in allocation ranges from 0.8 % to 100 %. programming a port ? s rate value to zero disables transmissions from that port and causes the transmit circuitry to ignore fifo flag indications from that port. the programmed rate value is an upper bound on the transmission from a particular port, and the exact ratio may not be achieved if multiple ports are active at the same time. 2.7.4 receive port addressing received cells are routed to each of the four fifo ports depending on the values in the header value and header mask registers. these registers allow a range of atm cells to be routed to one of the four fifo ports. also, the same atm cell can be routed to multiple receive fifo ports if desired. the hdr_valx_12 and hdr_valx_34 register contents are used to match incoming atm cell headers. there are four sets of these registers (x = 0, 1, 2, 3), one set for each of the four receive fifo ports. if hdr_valx_12 and hdr_valx_34 are a bitwise match to the incoming cell, then this cell is routed to the x receive fifo port.
2.0 functional description cn8223 2.7 fifo port/utopia interface atm transmitter/receiver with utopia interface 2-42 conexant 100046c 2.7.4.1 header screening the hdr_mskx_12 and hdr_mskx_34 registers further qualify the bitwise values in the header value registers. there are four sets of these registers (x = 0, 1, 2, 3), one set for each of the four receive fifo ports. a bit set to 1 in a header mask register sets the same bit position in the header value register to a don ? t care condition for accepting cell headers. an example of header value and mask register screening for cells received by fifo port 0 follows: hdr_val0_12 = 0000 h hdr_val0_34 = f000 h hdr_msk0_12 = 0000 h hdr_msk0_34 = 0000 h this header screening setup for fifo port 0 receives cells with octets 1 2 3 4 equal to 00 00 f0 00. since the header mask bits for port 0 are all 0, there is no effect on the header value screening. in the following example the header mask value allows multiple cells to be accepted by fifo port 0: hdr_val0_12 = 0000 h hdr_val0_34 = f000 h hdr_msk0_12 = 0000 h hdr_msk0_34 = 0003 h this header screening setup for fifo port 0 accepts four different received cells with octets 1 2 3 4 equal to 00 00 f0 00, 00 00 f0 01, 00 00 f0 02, or 00 00 f0 03. the 2 bits set in hdr_msk0_12 set don ? t care conditions for the same 2 bit positions in hdr_val0_12. this allows four different atm cell headers to be accepted by fifo port 0. these control registers enable the cn8223 to be programmed to accept only certain slot types, or all slots whether busy or not, and also to screen slots for a particular vci/vpi pattern. to disable header screening completely, write the mask register to all 1s. headers are screened after any error correction is performed by the hec circuitry. 2.7.4.2 output screening the receiver circuitry contains buffer storage so that the header octets can be examined to determine which, if any, port is to be activated for output. this allows output of the plcp and header octets in 57- and 53-octet modes, respectively. header octets are compared to the programmed values in the hdr_val registers under control of the hdr_msk registers. if a match is made, the data write strobe for that port is activated, and the cells are written to the port. by using the mask bits to mark don ? t care locations, cells with different header values can be sent to a single port. this allows entire vci/vpi ? pages ? to be sent to the same location. also, several ports can be programmed to receive cells with the same header values or overlapping pages of header values resulting in a programmable broadcast capability. if accept/reject [bits 15 ? 12] in config_3 [0x02], is set for a particular port, then all cells with headers matching the programmed header value and mask criteria are rejected by the port, and all other cells are accepted for output. this feature can be used to screen certain vci/vpi values from being output to a particular port.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.7 fifo port/utopia interface 100046c conexant 2-43 if delete idle cells [bit 2] of config_4 [0x29] is set, then received cells matching the idle header and mask criteria are automatically screened from appearing on the output of all ports. this idle cell screening is in addition to any reject values that are programmed for the individual ports. only addressed ports have active strobes. 2.7.5 utopia interface the cn8223 incorporates an interface that is compliant with both the atm forum utopia level 1 (version 2.01) specification and the saturn compliant interface for atm phy devices specification. when the utopia interface is enabled, the cn8223 becomes a single port device with all input and output of cell data taking place on port 0. configurations for ports 1, 2, and 3 (such as header values and masks or rate controls) are ignored when in utopia mode. the header values, masks, rate controls, and other per-port configuration control bits for port 0 govern the operation of the utopia port cell stream. the utopia interface contains transmit and receive buffer fifos with a depth of four cells and is programmable for reduced latency requirements per atm forum document 94/0317. utopia interface pins are listed in table 2-27 . the utopia interface is controlled by 0x2b?utopia_1 (utopia port control register 1) and 0x2c?utopia_2 (utopia port control register 2) . the timing for the utopia interface is functionally compatible with the timing shown in the version 2.01 atm forum specification. detailed timing information can be found in chapter 4.0 . table 2-27. utopia interface pins utopia signal cn8223 pin signal direction relative to cn8223 txdata (7:0) fdat_in[7:0] in txprty 0 fdat_in[8] in txsoc fctrl_in[0] in txenb~ fctrl_in[1] in txclk fctrl_in[2] in txfull~/txclav fctrl_out[2] out rxdata (7:0) fdat_out[7:0] out rxprty 0 fdat_out[8] out rxsoc fctrl_out[0] out rxenb~ fctrl_in[3] in rxclk fctrl_in[4] in rxempty~/rxclav fctrl_out[1] out ? fctrl_in[5:7] reserved, connect to ground ? fctrl_out[16:4] undefined output rcvfifooverflow fctrl_out[3] out
2.0 functional description cn8223 2.8 feac channel and hdlc data link programming atm transmitter/receiver with utopia interface 2-44 conexant 100046c 2.8 feac channel and hdlc data link programming this section discusses the use and programming requirements for the feac channel and hdlc data link. the feac channel is used in ds3 mode; the hdlc data link is used by ds3, e3, and sts-1/3 framers. 2.8.1 feac channel transmitter the feac channel transmitter is under control of the phy type [bits 2 ? 0], external framer [bit 5] of config_1 [0x00], transmit alarm control [bits 9 ? 4 of config_2 [0x01], enable feac transmission [bit 9], and transmit feac data [bits 15 ? 10] of txfeac_errpat [0x03]. an interrupt for use with feac channel operations is available on the dl_int output pin, and status bits for determining the interrupt source are located in the rxfeac_ver register [0x3c]. the phy type must be set to internal ds3 for feac channel transmission to take place. in ds3 mode, the last c bit in subframe 1 of the m-frame is used for transmission. setting the transmit alarm control [bits 9 ? 4] for transmission of ais disables transmission of the feac channel. transmission of yellow alarm or idle code has no effect on feac channel transmission. the txfeac_errpat register controls the byte to be transmitted on the feac channel. all messages for transmission on the feac channel must be in the form ? 0xxxmmm011111111 ? . the right-most bit of this sequence is the first bit transmitted on the channel. to initiate transmission of a message byte in the feac channel, write the desired byte in the form ? mmmxxx ? into bits 15 ? 10 of the txfeac_errpat register. a 1 must be written to enable feac transmission [bit 9]. transmission of the flag (11111111) and the 0s on either side of the ? xxxmmm ? pattern is automatic. ten repetitions of the message are sent before an interrupt is issued on the dl_int pin. the interrupt also appears in the rxfeac_ver register to request a new byte from the processor. to clear the interrupt, you must write the txfeac_errpat register. each time a new byte is written, 10 transmissions of that byte (and flag) will automatically occur. interrupts from the transmit feac channel will occur at a rate of approximately one interrupt per 17 ms. if you write a 0 to enable feac transmission [bit 9], then continuous transmission of idle flags is enabled and no interrupts are issued until a byte of the proper format is written to the txfeac_errpat register. interrupts from the feac channel transmitter appear on transmit feac interrupt [bit 8] in the rxfeac_ver register [0x3c].
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.8 feac channel and hdlc data link programming 100046c conexant 2-45 2.8.2 feac channel receiver the feac channel receiver is under control only of the received data stream. the receiver interrupt is under control of enable receive feac interrupt [bit 8] in txfeac_errpat. this interrupt must be enabled by setting this bit for receiver interrupts to appear on the dl_int output and for proper interaction with the processor. the last c bit in subframe 1 in c bit parity mode is provided to the receiver circuitry at all times. receiver status is monitored via receive feac interrupt [bit 9] in rxfeac_ver. when a receive feac channel interrupt is generated on dl_int, the receive feac interrupt bit will be set in 0x3c. if this bit is observed upon reading the rxfeac_ver, then at least 10 repetitions of the same byte have been received by the data link and placed in bits 15 ? 10 of rxfeac_ver. the receive interrupt serves as notice that the message bits in rxfeac_ver are valid. reading rxfeac_ver clears the receive interrupt. an idle message is all 1s, and all other messages are of the form ? 0xxxmmm011111111 ? with reception of the rightmost bit first from the channel. the receiver logic recognizes the eight 1s message flag followed by a message byte and interrupts the controller upon reception of 10 repetitions of a valid message byte. the ? mmmxxx ? message byte that was received is stored in rxfeac_ver bits 15 ? 10 at 0x3c. continuous incoming messages on the feac channel produce an interrupt rate of approximately one interrupt per 17 ms for this interrupt source. no interrupts are generated if the feac channel is receiving continuous idle flags or if the interrupt is not enabled in txfeac_errpat. 2.8.3 hdlc data link transmitter the hdlc data link capability is present in the following formats: ds3 terminal data link c bits g.751 e3 n bit g.832 e3 and e4 gc octet sts-1/sts-3c/stm-1 d1, d2, d3 octet data link the hdlc formatter has an 8-octet buffer (organized as four 16-bit words) for both the receiver and transmitter, located at addresses 0x58 through 0x5b and 0x5c through 0x5f, respectively. addresses are word-wide locations that hold 2 bytes each. therefore, each buffer has an address range of 4, two for each buffer half. each buffer holds 4 octets. the hdlc data link transmitter is under the control of the enable hdlc data link [bit 5] in the config_5 [0x31] and bits 6 ? 0 in dl_ctrl_stat [0x60]. an interrupt for use with data link operations is available on the dl_int output pin, and status bits for determining the interrupt source are located in dl_ctrl_stat. if the framer is in a mode that allows data link transmission as described above, the dl_ctrl_stat register is the main control register used for transmit data link operations. disable data link transmission [bit 6] of dl_ctrl_stat must be set low to enable operation of the data link. if this bit is set high, an all 1s signal is transmitted in the data link bit positions in the outgoing serial stream. with the data link enabled, the send message [bit 0], send fcs [bit 1], and abort message [bit 2] bits of dl_ctrl_stat control operation. txbytes[2:0] [bits 5 ? 3] of dl_ctrl_stat form a pointer to the tx_dl_buffer used by the data link transmitter.
2.0 functional description cn8223 2.8 feac channel and hdlc data link programming atm transmitter/receiver with utopia interface 2-46 conexant 100046c the transmitter implements an hdlc data link per itu standard q.921. the functions provided by the data link transmitter circuitry are transparency zero stuffing, frame check sequence (fcs) generation, idle flag generation, and abort flag generation. there are no restrictions on the total length of the message. q.921 requires that all messages be an integral number of 8-bit bytes. the transmitter can only transmit 8-bit bytes. the byte transmission times for the transmitter are approximately those shown in table 2-28 . an 8-byte buffer (organized as four 16-bit words) is provided for the transmit data link channel to minimize processor interruptions. this buffer is located at addresses 0x5c through 0x5f. byte 0 is the least significant byte of 0x5c, byte 1 is the most significant byte of 0x5c, byte 2 is the least significant byte of 0x5d, etc. filling of this buffer is accomplished by the processor in the same manner as writing to control registers. this buffer can be read as well as written to verify contents. the buffer is divided into two halves to reduce the real-time requirements on the processor. the processor loads four bytes (2 words) at a time, while the data link transmitter reads from the other half of the buffer. this gives the processor at least 160 s (at the fastest byte rate) to assemble the next four bytes of message for transmission before the next interrupt is issued. interrupts are issued each time the transmitter circuitry reaches a 4-byte buffer boundary. the transmitter should be initialized with the dl_ctrl_stat register bits 6 ? 0 written to zero. this enables the transmitter to send idle flags on the data link. no interrupts are generated when the data link is sending idle flags, thus no processor intervention is required until a message is to be sent. 2.8.3.1 sending a message beginning with an idle channel, the processor writes the first four bytes of message data to the tx_dl_buffer. the first two bytes of data to be transmitted should be written to 0x5c. the message is written to the buffer in ascending order starting at 0x5c and ending at 0x5f. the least significant bit (lsb) in each byte is transmitted first. this buffer can be written well before the message is to be sent, if desired. after the first block of data is present in the buffer memory, the processor writes to the dl_ctrl_stat register to begin transmission: send message = 1 txbytes[2:0] = 3 send fcs = 0 abort message = 0 table 2-28. byte transmission times for transmitter mode byte transmission times ds3 c bit parity 284 s g.751 e3 357 s g.832 e3, e4 125 s sts-1 125 s sts-3c/stm-1 42 s
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.8 feac channel and hdlc data link programming 100046c conexant 2-47 the 3-bit field txbytes[2:0] is functionally split into two parts. the most significant bit (msb) indicates to the transmitter circuitry which half of the buffer to read from next. the two lsbs indicate the stop location, i.e., where the last message byte is located. when the new controls are latched by the transmitter circuitry, the processor is interrupted for the next set of controls. now, the processor has up to 4-byte intervals (byte transmission time periods) to write a new set of controls to the control register. because of a race condition, the isr that is processing the transmit interrupt must delay 1.5 byte times before writing a new control register value. the processor can now write the next block of data to the next half of the message buffer. when the end of a message is reached, or in the event of a short message, there may not be exactly 4 bytes remaining. in this case, the processor writes the remaining data to the message buffer as usual. the processor now must write the highest location used to the txbytes[2:0] field in the data link control register. send fcs is set to 1. this causes the fcs to be sent after this last block of data. when this set of controls is latched, the processor is interrupted. at this time a new message can be sent, or send message can be set to 0 to send idle flags. if a new message is to be sent immediately, the next half of the transmit buffer can be written, and the data link control register configured accordingly. this results in only one idle flag being transmitted between messages. if there is no new message ready, the processor must write send message to 0. if this is not done within 4 byte intervals, undefined data is transmitted. 2.8.3.2 aborting a message to abort a message in progress, the controller writes abort message to 1 in the data link control register. the transmitter finishes sending the message byte in progress, then transmits an abort flag (11111110). after writing the abort signal to the control register, a second write may follow the next interrupt to cause the transmitter to go to the idle condition or to transmit another message. in the latter case, the abort flag is followed by one idle flag, and the new message begins. if the second write is not performed, the formatter continues to transmit abort flags until instructed otherwise. 2.8.3.3 transmitter interrupts the transmitter generates an interrupt when it has latched the present set of controls and is ready for a new set. there are no interrupts during the transmission of idle flags. therefore, to start a message from an idle condition, the processor writes the first half of the buffer and the proper control bits. when the circuit latches these controls internally, an interrupt is immediately issued for the next set of control bits. the processor then has up to 4 byte intervals to respond to the interrupt. the interrupt appears on the dl_int pin. the dl_ctrl_stat register indicates the source of the interrupt but not the cause. the controller software must know from the message context what response is required. the interrupt is an active low level, not a pulse. the transmit interrupt is cleared upon the writing of the dl_ctrl_stat register. a write operation must be performed to clear the current interrupt and prevent missing later interrupts. if the interrupt is a mid-message interrupt, a new data link control word must be written with txbytes[2:0] equal to the ending location of the next message block. the msb of txbytes[2:0] informs the transmit circuitry which half of the buffer to read next. interrupts from the hdlc data link transmitter will appear on transmitter interrupt [bit 14] in dl_ctrl_stat [0x60]. interrupts must be enabled to appear on dl_int by setting enable hdlc data link = 1 in config_5.
2.0 functional description cn8223 2.8 feac channel and hdlc data link programming atm transmitter/receiver with utopia interface 2-48 conexant 100046c 2.8.3.4 transmitter control example this example shows the sequence necessary to transmit a 10-byte hex message starting in the low half of the transmit buffer. with the transmitter in the idle state, the processor executes the following sequence: write bytes 1 and 2 to address 0x5c write bytes 3 and 4 to address 0x5d write 19 to address 0x60 (bytes = 3, send message = 1) at tx interrupt: write bytes 5 and 6 to address 0x5e write bytes 7 and 8 to address 0x5f write 39 to address 0x60 (bytes = 7, send message = 1) at tx interrupt: write bytes 9 and 10 to address 0x5c write 0b to address 0x60 (bytes = 1, send message = 1, send fcs = 1)at tx interrupt: write 00 to address 0x60 (send message = 0, send fcs = 0 2.8.4 hdlc data link receiver the hdlc data link receiver is under the control of the received data stream only. the receiver interrupt is under the control of enable receive data link interrupt [bit 7] in dl_ctrl_stat [0x60]. you must enable this interrupt by setting this bit for receiver interrupts to appear on the dl_int output and for proper interaction with the processor. the hdlc data link capability is present in the following formats: ds3 terminal data link c bits g.751 e3 n bit g.832 e3 and e4 gc octet sts-1/sts-3c/stm-1 d1, d2, d3 octet data link the data link bits are provided to the receiver circuitry at all times. therefore, when the line_status register [0x38] indicates that alarms are being received that render the data link information useless, you can disable the receive data link interrupt to prevent excessive or spurious interrupts to the processor. receiver status is monitored via receiver interrupt [bit 15] in dl_ctrl_stat and via the receiver status bits in that register (bits 13-8). when a receive data link interrupt is generated on dl_int, the receiver interrupt bit is set. if this bit is observed upon reading the dl_ctrl_stat register, then the status obtained from bits 13 ? 8 indicates the receiver status that caused the interrupt. the dl_ctrl_stat register contains three status bits and a three-bit buffer pointer. the status bits are abort flag received [bit 8], bad fcs [bit 9], and idle code received [bit 10]. the 3-bit buffer pointer rxbytes[2:0] [bits 13 ? 11] is used to point to locations in the 8-byte (organized as four 16-bit words) rx_dl_buffer. this buffer is located at addresses 0x58 through 0x5b. the buffer pointer indicates the last location written by the data link receiver. byte 0 of the buffer is the least significant byte of 0x58, byte 1 is the most significant byte of 0x58, byte 2 is the least significant byte of 0x59, etc.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.8 feac channel and hdlc data link programming 100046c conexant 2-49 2.8.4.1 receiver operation the receiver implements an hdlc data link per itu standard q.921. the functions provided by the data link receiver circuitry are transparency-zero removal, fcs checking, idle flag reception, and abort flag reception. there are no restrictions on the total length of the message. q.921 requires that all messages be an integral number of 8-bit bytes. if the receiver receives a message that is not an integral number of bytes, the receiver status indicates a message received with bad fcs. the per-byte reception times are equivalent to those given for the transmitter for any particular mode. the receiver powers up in an indeterminate state. it is initialized by the receipt of an idle flag (0x7e) on the link, which sets idle code received = 1 in the data link status register (bits 13-8 of 0x60). when the idle flag is removed from the link and a message starts coming in, the receiver removes stuffed 0s and writes the resulting data to the receive data link buffer beginning with the least significant byte of 0x58 and counting up to the most significant byte of 0x5b. when the first four bytes have been written, the processor is interrupted to read the data out of the buffer. the processor has 4 byte intervals to read the data before it is overwritten with new data. the interrupt is cleared when the processor reads dl_ctrl_stat. the status register indicates a message in progress at this time: idle code received = 0 rxbytes[2:0] = 3 if the upper half of the buffer had just been filled, the status register indicates rxbytes[2:0] = 7, and locations 4 through 7 must be read during the next 4 byte intervals to retrieve the message. when the last block of data has been received, the processor is again interrupted. this time, the data link status register indicates the end of message: idle code received = 1 rxbytes[2:0] = n bad fcs = 0 or 1 the rxbytes[2:0] = n portion of the register indicates the highest-numbered location that was written in the receive buffer. locations 0 to n or 4 to m (where n = 0 to 3 and m = 4 to 7) must be read to retrieve the data depending on what has already been read at the previous interrupt. the two highest-numbered locations contain the fcs that was received at the end of the message. a new incoming message always starts in the opposite buffer half from where the previous message ended to prevent overwriting of previously received bytes and allow the processor time to retrieve those bytes. for example, if a message ended in buffer 0x5a or 0x5b, the next message received would be stored starting in 0x58. if a message ended in buffer 0x58 or 0x59, the next message received would be stored starting in 0x5a. if the received message is a multiple of 8 bytes, then when the processor is interrupted to read the last block of data, the fcs has yet to be received. in this event, the processor is again interrupted when the fcs has been checked, and an idle flag received. the data link status register shows rxbytes[2:0] = 1 (or 5), fcs good or bad, and idle code received = 1; and the fcs that was received will be in locations 0 and 1 (or 4 and 5). again, the data must be read out during the next 4 byte intervals, or it may be overwritten by a new incoming message.
2.0 functional description cn8223 2.8 feac channel and hdlc data link programming atm transmitter/receiver with utopia interface 2-50 conexant 100046c alternatively, the fcs data may be ignored, and the good or bad indication used directly. it is important that software strategies allow for the fact that the lapd receiver cannot recognize the fcs as such until the closing flag is recognized. it can happen that the processor is interrupted to read 4 message bytes, and the next byte received is the closing flag. when the processor exits the interrupt routine, another interrupt will be pending for the end of message. the status for this interrupt indicates the idle condition, the fcs status, and the byte count will be the same as the previous interrupt (rxbytes[2:0] = 3 or 7) because no extra bytes were received. in this event, the last two bytes read from memory on the previous interrupt were not message bytes after all, but were actually the fcs bytes. if the fcs spans a 4-byte boundary, the final interrupt indicates that one additional byte was received (rxbytes[2:0] = 0 or 4), the idle condition, and the fcs status. 2.8.4.2 receiver interrupts the data link receiver generates an interrupt in response to three events: 1. the current half of the message buffer is full 2. the end-of-message flag was detected 3. an abort flag was detected dl_ctrl_stat indicates the cause of the interrupt. the interrupt is cleared upon the reading of this register. if the interrupt is due to the current half of the receive buffer being full, idle code received is cleared, and rxbytes[2:0] indicates which half of the buffer must be read. if the interrupt is due to the end-of-message flag being detected, idle code received is set, bad fcs indicates the result of the fcs error check, and rxbytes[2:0] indicates the last location written. the processor is not interrupted again until four bytes of a new message have been received. if the interrupt is due to an abort flag being received, abort flag received is set, and there is nothing to be done by software other than discard any previously received message bytes. the processor will not be interrupted again until four bytes of a new message have been received. interrupts from the hdlc data link receiver appear on receiver interrupt [bit 15] in dl_ctrl_stat. interrupts must be enabled to appear on dl_int by setting enable receive data link interrupt [bit 7] in dl_ctrl_stat.
cn8223 2.0 functional description atm transmitter/receiver with utopia interface 2.8 feac channel and hdlc data link programming 100046c conexant 2-51 2.8.5 receiver response example the following example shows the sequence necessary to receive an 8-byte hex message that was stored starting in the low half of the receive buffer. in this example, the final interrupt indicates that two more bytes are present in the buffer; however, these bytes are fcs bytes, not message bytes. when an interrupt is received, the processor reads dl_ctrl_stat [0x60] to determine the source of the interrupt. if the source is determined to be the receive hdlc data link, the processor responds in the following manner (the status shown below ignores bits 15 and 14 in dl_ctrl_stat): at rx interrupt: read address 0x60 to get status (status = 18xx: bytes = 3, idle = 0) read address 0x58 to get 1st and 2nd data bytes read address 0x59 to get 3rd and 4th data bytes at rx interrupt: read address 0x60 to get status (status = 38xx: bytes = 7, idle = 0) read address 0x5a to get 5th and 6th data bytes read address 0x5b to get 7th and 8th data bytes at rx interrupt: read address 0x60 to get status(status = 0cxx or 0exx bytes = 1, idle = 1, bad fcs = 0 or 1) read address 0x58 if desired (fcs bytes 1 and 2)
2.0 functional description cn8223 2.8 feac channel and hdlc data link programming atm transmitter/receiver with utopia interface 2-52 conexant 100046c
100046c conexant 3-1 3 3.0 registers 3.1 registers overview table 3-1 displays an overview of the cn8223 registers. all registers are 16-bit, and the addresses are on 16-bit boundaries. there are seven address pins, a[7:1]. a[0] is always 0; therefore, it does not require a pin. table 3-1. atm transmitter/receiver status registers, counters, and data link control cn8223 control and status registers address name allowed operations 0x00 ? 0x31, 0x60 control registers read and write 0x38 ? 0x3b status registers read only 0x3c part number/version/feac rx read only 0x40 ? 0x48 line framer/phy error counters read only 0x49 ? 0x4d cell error counters read only 0x4e ? 0x57 cell transmitted/received counters read only 0x58 ? 0x5b receive hdlc data link buffers read only 0x5c ? 0x5f transmit hdlc data link buffers read and write
3.0 registers cn8223 3.2 control register overview atm transmitter/receiver with utopia interface 3-2 conexant 100046c 3.2 control register overview table 3-2 lists the 52 control registers of the cn8223. control registers are realized as latches within the cn8223 and are programmed by a write operation from the microprocessor. no initialization is provided for operational purposes. all registers must be initialized as required for each application by the microprocessor. a reset signal on the reset pin (pin 118) resets counters and framer state machines. reset does not affect control register contents. control bits that do not have a defined function are reserved and must be written to 0. all control registers can be read to verify contents, except those control bits whose functions cause single events and are, therefore, not latched. control registers in this section have been ordered by function: 7 control configurations, 19 control transmitter functions, 22 control receiver functions, and 4 enable interrupts. table 3-2. atm transmitter/receiver microprocessor control registers (1 of 2) address name function 0x00 config_1 configuration control register 1 0x01 config_2 configuration control register 2 0x02 config_3 configuration control register 3 0x03 txfeac_errpat transmit feac/bip-8 error pattern 0x04 cell_gen_0 cell generation control - port 0 0x05 cell_gen_1 cell generation control - port 1 0x06 cell_gen_2 cell generation control - port 2 0x07 cell_gen_3 cell generation control - port 3 0x08 tx_rate_23 transmit rate control value - ports 2, 3 0x09 tx_rate_01 transmit rate control value - ports 0, 1 0x0a tx_idle_12 transmit idle header value - octets 1, 2 0x0b tx_idle_34 transmit idle header value - octets 3, 4 0x0c tx_hdr0_12 transmit port 0 header value - octets 1, 2 0x0d tx_hdr0_34 transmit port 0 header value - octets 3, 4 0x0e tx_hdr1_12 transmit port 1 header value - octets 1, 2 0x0f tx_hdr1_34 transmit port 1 header value - octets 3, 4 0x10 tx_hdr2_12 transmit port 2 header value - octets 1, 2 0x11 tx_hdr2_34 transmit port 2 header value - octets 3, 4 0x12 tx_hdr3_12 transmit port 3 header value - octets 1, 2 0x13 tx_hdr3_34 transmit port 3 header value - octets 3, 4 0x14 cell_val cell validation control 0x15 hdr_val0_12 receive port 0 header value - octets 1, 2
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.2 control register overview 100046c conexant 3-3 0x16 hdr_val0_34 receive port 0 header value - octets 3, 4 0x17 hdr_val1_12 receive port 1 header value - octets 1, 2 0x18 hdr_val1_34 receive port 1 header value - octets 3, 4 0x19 hdr_val2_12 receive port 2 header value - octets 1, 2 0x1a hdr_val2_34 receive port 2 header value - octets 3, 4 0x1b hdr_val3_12 receive port 3 header value - octets 1, 2 0x1c hdr_val3_34 receive port 3 header value - octets 3, 4 0x1d hdr_msk0_12 receive port 0 header mask - octets 1, 2 0x1e hdr_msk0_34 receive port 0 header mask - octets 3, 4 0x1f hdr_msk1_12 receive port 1 header mask - octets 1, 2 0x20 hdr_msk1_34 receive port 1 header mask - octets 3, 4 0x21 hdr_msk2_12 receive port 2 header mask - octets 1, 2 0x22 hdr_msk2_34 receive port 2 header mask - octets 3, 4 0x23 hdr_msk3_12 receive port 3 header mask - octets 1, 2 0x24 hdr_msk3_34 receive port 3 header mask - octets 3, 4 0x25 rx_idle_12 receive idle header value - octets 1, 2 0x26 rx_idle_34 receive idle header value - octets 3, 4 0x27 idle_msk_12 receive idle header mask - octets 1, 2 0x28 idle_msk_34 receive idle header mask - octets 3, 4 0x29 config_4 configuration control register 4 0x2a idle_pay transmit idle cell payload value 0x2b utopia_1 utopia port control register 1 0x2c utopia_2 utopia port control register 2 0x2d en_line_int line/phy status interrupt enable register 0x2e en_event_int status event interrupt enable register 0x2f en_ovfl_int counter overflow interrupt enable register 0x30 en_cell_int cell counter interrupt enable register 0x31 config_5 configuration control register 5 0x32 tx_k1k2 transmit k1, k2 value for sonet aps 0x33 rx_k1k2 receive k1, k2 value for sonet aps 0x60 dl_ctrl_stat hdlc data link control and status register table 3-2. atm transmitter/receiver microprocessor control registers (2 of 2) address name function
3.0 registers cn8223 3.3 configuration control registers atm transmitter/receiver with utopia interface 3-4 conexant 100046c 3.3 configuration control registers 0x00?config_1 (configuration control register 1) the config_1 register is located at address 0x00. this register sets chip parameters for both transmit and receive operations. the line interface type is set for both transmit and receive by bits 7 ? 0. valid combinations of bits 7 ? 0 for the line interface type in this register are given in table 3-3 . bit field size name description 15 1 sts-1 stuffing option enables an alternate atm mapping for sts-1 mode. if this bit is set, then 84 columns of the spe are available for atm cell octets. if this bit is not set, then all 86 columns of the spe are available for atm cell octets. 14 1 source loopback causes the receiver input to be taken from the transmitter output in all modes; the transmitter output is unaffected. this function allows the generation of self-diagnostic routines at system startup to ensure the health of the line/physical framing process. if an external framer mode is selected, the external framer needs to continue providing an input to txsyi when source loopback is enabled. source loopback does not work in taxi mode. 13 1 enable one-second latching of line counters causes status indications in the line/phy counters (other than lcv) to be latched at one-second intervals. this interval is determined by successive rising clock edges to oneseci. if an alarm condition is present during a one-second interval, it is available to be read on the successive interval. otherwise, the status is latched and held until it is read. if this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears it. 12 1 enable one-second latching of line status causes status indications in the line_status register to be latched at one-second intervals. the one-second interval is determined by successive rising clock edges to oneseci. if an alarm condition is present during a one-second interval, it is available to be read on the successive interval. otherwise, the status is latched and held until it is read. if this bit is set and the status word is read twice within a one-second interval, the second read gives the current state of the status word and clears it. 11 1 external 8 khz timing forces the transmit plcp to be synchronized to an external 8 khz timing reference rather than to the received plcp reference. this control bit is meaningful only in 57-octet ds3 and e3 formats. 10 1 receiver hold enable allows the rcv_hld input to disable cell processing. internal cell receiver functions will operate, but no segments will be accepted by the cell validation state machine or output on the fifo ports. 91enable cell scrambler enables the x 43 + 1 scrambler (required for 53-octet direct mapping) for cell payload. 8 1 disable locd allows cell validation and error counting to continue when cell delineation is lost (via either plcp or hec).
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.3 configuration control registers 100046c conexant 3-5 71enable hec alignment enables cell delineation via the hec alignment method. this method is for use in any mode where cells are directly mapped into the physical layer. when this bit is set, 53-octet cells are expected. when this bit is low, 57-octet cells (with plcp framing overhead) are expected. 6 1 enable parallel interface selects the parallel interface for input/output. when this bit is low, serial data is expected; when high, parallel data is expected. 5 1 external framer set if line framing is performed with an external framer. when this bit is low, the internal framer for the selected mode will be used. 4 1 disable b3zs/hdb3 bypasses the internal encoder/decoder so that nrz data can be presented directly to the internal framing functions. for e1 and ds1 in external framer mode, set to 0. 3 1 unframed input specifies whether the serial stream from an external circuit contains overhead or only payload. the normal mode is framed mode. physical layer overhead bits are located by a synchronization input and are ignored by the phy framer. in unframed mode, all line framing bit positions are assumed to be nonexistent. 2 ? 0 3 phy type sets the type of line framing and physical processing to be used. phy modes are always symmetric; the transmit and receive modes are identical. the plcps for ds1 and ds3 are described in tr-tsv-000773; e1 and e3 plcps are described in etsi draft standards prets 300 213 and prets 300 214; e3, ds3, and e4 direct-mapped modes are described in itu g.832; and sts-1 and sts-3c formats are described in tr-nwt-000253. bit field size name description
3.0 registers cn8223 3.3 configuration control registers atm transmitter/receiver with utopia interface 3-6 conexant 100046c table 3-3. valid combinations of config_1, bits 0 ? 7 type of line input signal phy type unframed input disable b3zs/ hdb3 external framer enable parallel interface enable hec align ds1 00 0100 or 1 ds1 (externally gapped 192 bits/frame) 0 1 0 1 0 0 e1 10 0100 or 1 e1 (externally gapped ts0 and ts16) 1 1 0 1 0 0 ds3, internal framer 2 0 0 or 1 0 0 0 or 1 ds3, external framer 2 0 0 1 0 0 or 1 ds3, external framer (gapped 84/85 bits) 2 1 0 1 0 0 e3, internal g.751 format 3 0 0 or 1 0 0 0 e3, external g.751 format 3 0 0 1 0 0 e3, external g.751 format (gapped 1st 16 bits) 31 0100 e3, internal g.832 format 4 x 0 or 1 0 0 1 e4, internal g.832 format 5 x 1 0 0 1 sts-1, internal framer 6 x 0 or 1 0 0 1 sts-3c/stm-1, internal framer 7 x 1 0 0 1 parallel or taxi interface, 53 octet cells 0 x 0 1 1 1 notes: 1. ? x ? = don ? t care
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.3 configuration control registers 100046c conexant 3-7 0x01 ? config_2 (configuration control register 2) the config_2 register is located at address 0x01 and controls transmit formatting and alarm generation. table 3-4 defines alarm controls for the line framing/phy formats. table 3-5 defines the control bits for sts-1/sts-3c/stm-1. table 3-6 defines the overhead bits for line framing/phy formats. bit field size name description 15 1 enable external overhead enables all overhead octets to be inserted externally in sts-1/sts-3c/stm-1 and g.832 e3/e4 modes. if this bit is not set, internal generation of overhead octets is enabled as described in section 2.3 . 14 1 all-zeros febe inserts an all-0s value in the febe field. the all-0s value provides an indication at the far end that no bip-8 errors are being detected. bip-8 status and error counts are not affected. this control bit is active in all modes whether the febe field is single- or multi-bit. 13 1 all-1s febe inserts an all-1s value in the febe field of the transmit frame. the all-1s value notifies the far end that the febe function is inhibited. bip-8 status and error counts are not affected. this control bit is active in all modes whether the febe field is single- or multi-bit. 12 ? 10 3 bip error insert selects the bip field that will be errored with the txfeac_errpat register according to the following: these bits are cleared by the transmitter after the error is inserted in the overhead field, and can be read as 0 to verify that error insertion has taken place. 9 ? 4 6 transmit alarm control controls the generation of alarms for 57-octet plcps and internal framers. no alarms are transmitted if all bits in this control field are set to 0. setting any of these bits to a 1 causes an alarm to be transmitted according to table 3-4 and table 3-5 . for example, in sts-3c mode, setting bit 4 to a 1 will cause the line ais alarm to be transmitted. 3 ? 0 4 overhead control selectively disables overhead generation. standard overhead is generated internally if all bits in this control field are set to 0. overhead sources for all phy modes are given in table 2-8 . when a particular overhead field is set to be disabled, it will be filled with 0s. overhead generation is disabled dependent on mode, according to the data in table 3-6 . bit 12 bit 11 bit 10 bip field to be errored 0 0 0 no errors inserted 0 0 1 b1 field (all modes) 0 1 0 b2 field, bits 23:16 (sts-3c/stm-1 mode only) 0 1 1 b2 field, bits 15:8 (sts-3c/stm-1 mode only) 1 0 0 b2 field, bits 7:0 (sts-1/sts-3c/stm-1 modes) 1 0 1 b3 field (sts-1/sts-3c/stm-1 modes) 1 1 0 no errors inserted 1 1 1 b2 field, all 3 octets (sts-3c/stm-1 mode)
3.0 registers cn8223 3.3 configuration control registers atm transmitter/receiver with utopia interface 3-8 conexant 100046c table 3-4. alarm transmission line framing/phy format alarm control 7 alarm control 6 alarm control 5 alarm control 4 53-octet ds1, e1 modes not used not used not used not used 57-octet external (phy types 0 ? 3) g1 yellow (plcp) not used not used not used 57-octet internal ds3 mode g1 yellow (plcp) x-bit yellow idle code ais 57-octet internal g.751 e3 mode g1 yellow (plcp) a-bit yellow not used ais e3/e4 g.832 (phy types 4 ? 5) not used ma timing marker ma ferf ais 53-octet internal ds3 mode not used x-bit yellow idle code ais table 3-5. alarm transmission ? sts ? 1/sts ? 3c/stm ? 1 sts-1/sts-3c/stm-1 (phy types 6-7) alarm control bit line ais alarm control 4 line ferf alarm control 5 path yellow alarm control 6 path ferf alarm control 7 path ais alarm control 8 spe unequipped alarm control 9 table 3-6. overhead generation disable line framing/phy format overhead bit 3 overhead bit 2 overhead bit 1 overhead bit 0 57-octet modes (phy types 0 ? 3) a1, a2, pn b1 c1 trailer bits e3/e4 g.832 (phy types 4 ? 5) a1, a2 em ma not used sts-1/sts-3c/stm-1 (phy types 6 ? 7) a1, a2 b1, b2, b3 h1, h2, h3, h4 c1, c2
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.3 configuration control registers 100046c conexant 3-9 0x02 ? config_3 (configuration control register 3) the config_ 3 register is located at address 0x02 and controls miscellaneous functions. bit field size name description 15 ? 12 4 accept/reject header ? port 3 ? 0 allows each receive port to be programmed to either accept or reject cells with headers as specified in the rxhdr registers. when this bit is low, cells with headers matching the header value (as qualified by the mask value) for the port will be accepted and written out to the port. when this bit is high, cells with matching headers (as qualified by the mask value) will be rejected, and all other cells will be accepted and written out to the port. 11 1 count block errors changes the count function of error counters 5 ? 9 [0x44 ? 0x48]. when this bit is low, the counters count the actual number of errored bits in the bip or febe octets. when this bit is high, the counters increment once for each errored bip or febe block per g.826. 10 1 reserved set to 0. 9 1 line loopback enables a loopback of the incoming receive data and clock to the transmit data and clock outputs. the receive data is still processed by the receiver circuitry. invert tx clock output (bit 7) is functional in this mode to allow inversion of the looped clock at tclko (or tclko_hs). line loopback is not functional for taxi or external framer modes. upon a hardware reset (pin 118), this bit will be cleared (set to 0). 8 1 invert rx clock sampling selects the edge of the receive clock input where the incoming receive data is sampled. when this bit is low, the incoming data on rxin (or rxin_hs) is sampled by the falling edge of rxcki (or rxcki_hs). when this bit is high, the incoming data is sampled on the rising edge. this bit must be set for operation in taxi mode. 7 1 invert tx clock output selects the active edge of the transmit clock output when connecting directly to an external liu. when this bit is low, the falling edge of tclko (or tclko_hs) will be centered on the relevant data outputs. when this bit is high, the rising edge of tclko (or tclko_hs) will be centered on the data outputs. 6 1 for ds3 and g.751 e3 plcp modes: force nibble stuffing if this bit is low, 13/14 nibble stuffing is performed in ds3 and g.751 e3 plcp modes. stuffing is performed to synchronize the transmit plcp with either the external 8 khz frame reference or the receive plcp framer, depending on the setting of external 8 khz timing in the config_1 register. if this bit is high, the transmitter plcp framing is allowed to free-run to an internally generated 8 k frame rate when no clock is available from the 8 khz input or the receive plcp framer. this bit is ignored in modes that do not perform nibble stuffing. 6 1 for sts-3c and stm-1 modes: tx overhead control in sts-3c and stm-1 modes, this bit determines whether transmit overhead bytes g1, k2#1, and z2#3 are input from the transmit overhead bus or are internally generated. when this bit is set to 0 the following are internally generated: g1-path febe/rdi ? path febe is automatically generated in response to path bip errors. path rdi (yellow alarm) is inserted according to config_5, bits 2 and 3. k2#1 ? line ferf is transmitted by setting config_2 bit 5 to a 1. z2#3 ? line febe alarm is transmitted automatically in response to line bip errors. when this bit is set to 1, these bytes are obtained from the external txovh bus. 5 1 parity odd/even set to 1: odd parity fifo port generation and checking. set to 0: even parity fifo port generation and checking.
3.0 registers cn8223 3.3 configuration control registers atm transmitter/receiver with utopia interface 3-10 conexant 100046c 0x29 ? config_4 (configuration control register 4) the config_ 4 register is located at address 0x29 and controls miscellaneous functions. 4 1 check input parity enables parity checking at the fifo port inputs. this bit must be enabled for the input parity error status bits or interrupts to be active. 3 1 disable write strobes on invalid cells inhibits the receive port fifo write strobes when a cell is determined to be invalid for use with generic fifos. 21enable ds1 prs generator causes the physical layer data content to be replaced by a quasi-random signal stream. this stream is used for certain transmission tests in ds1 systems. 1 1 hec coverage determines the calculation range for the hec. if this bit is low, the hec is calculated over header octets 1 ? 4 for atm cells. if this bit is high, the hec is calculated over header octets 2 ? 4 for smds/802.6 cells. 01enable hec coset enables the x 6 + x 4 + x 2 + 1 polynomial to be xor ? ed with the calculated hec prior to transmission and prior to error detection/correction if hec is internally generated. for taxi mode, enable hec coset must be active. bit field size name description bit field size name description 15-12 4 disable crc check-ports 3 ? 0 disables the payload crc check on a per-port basis. this disable controls only the output of cells to the fifo interface and does not control the counting of payload crc errors. (counts are performed collectively, not per port.) 11-8 4 disable length check-ports 3 ? 0 disables the payload length check on a per-port basis. this disable controls only the output of cells to the fifo interface and does not control the counting of payload length errors. (counts are performed collectively, not per port.) 7-4 4 disable port reception-ports 3 ? 0 disables the output of any received cells on a per-port basis. this disable control is internally synchronized to cell boundaries so that no partial cells are output on a port. 31enable taxi interface enables an interface specific to 100 mbps 4b/5b data transceivers on the parallel interface port. this interface is detailed in section 2.5.1 . 2 1 delete idle cells allows the screening of cells matching the receive idle header and mask criteria from appearing on the outputs of any of the receive ports. when this bit is low, idle cells are not automatically screened from port output. when this bit is high, idle cells are screened from output on the receive fifo port. 1 1 enable external section trace allows the section trace octet (c1) to be inserted externally. when this bit is low, the c1 octet is generated internally. when this bit is high, the c1 octet is inserted from the txovh input bus. 0 1 stm-1/sts-3c pointer enables the ss bits to be generated in the au-4 pointer for stm-1 compatibility. when this bit is low, an sts-3c h1/h2 pointer is generated by the transmitter (no ss bits present) and the c2 octet (1) has the value 0x13. when this bit is high, an stm-1 au-4 pointer is generated with the ss bits set to 10. note(s): (1) the c2 octet is the sts path signal label. it is allocated to indicate the content of the sts spe, including the status of the mapped payloads.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.3 configuration control registers 100046c conexant 3-11 0x31 ? config_5 (configuration control register 5) the config_5 register is located at address 0x31 and controls miscellaneous functions. bits 3 ? 0 are control bits which can be written and read. bits 10, 9, and 8 are read-only status bits. bit field size name description 15 ? 11 5 reserved set to 0. 10 1 receive g1 bit 5 indicates the value of the rdi qualifier bit being received in the g1 octet of the sts-3c/stm-1 frame. this bit would be used in conjunction with bit 4 in the line_status register [0x38] to determine the type of rdi (path yellow) being received. 9 1 receive g1 bit 6 indicates the value of the rdi qualifier bit being received in the g1 octet of the sts-3c/stm-1 frame. this bit would be used in conjunction with bit 4 in the line_status register [0x38] to determine the type of rdi (path yellow) being received. 8 1 receive g1 bit 7 indicates the value of the rdi qualifier bit being received in the g1 octet of the sts-3c/stm-1 frame. this bit would be used in conjunction with bit 4 in the line_status register [0x38] to determine the type of rdi (path yellow) being received. 7 1 bt8222: reserved for bt8222b and higher including the cn8223: reset set to 0. in bt8222 revision b and higher, this bit is a software reset. writing this bit to 1 has the same affect as high logic level on pin 118, reset. 6 1 set g1 x bits all-1s sets the x bits in the g1 octet of the plcp overhead to all 1s when this bit is high. when this bit is low, the x bits will be all 0s. 5 1 enable hdlc data link enables the internal hdlc data link receiver and transmitter. programming for the hdlc data link is described in section 2.8 . 4 1 reserved set to 0. 3 1 transmit g1 bit 5 controls the transmission of the qualified rdi signals in the path status octet (g1) in sonet/sdh modes. the value written to this bit will be placed in the corresponding bit of the g1 octet. 2 1 transmit g1 bit 6 controls the transmission of the qualified rdi signals in the path status octet (g1) in sonet/sdh modes. the value written to this bit will be placed in the corresponding bit of the g1 octet. 1 1 enable external signal label selects the source for the c2 octet in the path overhead for sonet/sdh formats. when this bit is low, the c2 octet is internally generated. when this bit is high, the c2 octet is obtained from the txovh inputs. 0 1 transmit clock select selects the clock source for the transmitter circuitry. when this bit is low, the transmit clock is from the txcki or txcki_hs inputs. when this bit is high, the transmit clock is from the rxcki or rxcki_hs inputs to enable loop timing.
3.0 registers cn8223 3.3 configuration control registers atm transmitter/receiver with utopia interface 3-12 conexant 100046c 0x2b ? utopia_1 (utopia port control register 1) the utopia_1 register is located at address 0x2b and controls operation of the utopia interface. operation of the utopia interface is detailed in section 2.7.5 . bit field size name description 15 ? 7 9 reserved set to 0. 6 1 reset tx fifo resets the address generators and flags associated with the transmit fifo when this bit is set high. this bit should be set high when enable utopia interface (bit 0) is first set high, then written low after atm and phy layer initialization is complete. while the cn8223 is being initialized, its bit should be held low. before setting this bit high, the atm layer utopia interface control lines must be in an inactive state. if they are not, the cn8223 utopia fifo pointers could become corrupted. to conserve power, write this bit high if the utopia interface is not used. 5 1 reset rx fifo resets the address generators and flags associated with the receive fifo when this bit is set high. this bit should be set high when the enable utopia interface control bit is first set high and can then be written low after atm and phy layer initialization is complete. while the cn8223 is being initialized, this bit should be held low. before setting this bit high, the atm layer utopia interface control lines must be in an inactive state. if they are not, the cn8223 utopia fifo pointers could become corrupted. to conserve power, this bit should be written high if the utopia interface is not used. 4 1 reserved set to 0. 3, 2 2 flag threshold selects the cell look-ahead level for asserting the txfull~/txclav flag to the atm layer. the control bits and flag look-ahead are as follows: 1 1 octet/cell handshake selects the full flag handshake protocol for the fifo buffers. if this bit is low, then octet-level handshaking is selected and the flags supplied are txfull~ and rxempty~. if this bit is high, then cell-level handshaking is selected, and the flags supplied are txclav and rxclav. in octet-handshake mode, the rxclav flag goes active after one full cell is in the receive utopia fifo. also in this mode, when the 256-byte transmit utopia fifo has 252 bytes filled, txclav goes active, indicating that only four bytes of space remain. 0 1 enable utopia interface selects the interface type on the fifo i/o pins. if this bit is low, the interface is the standard four-port fifo interface. if this bit is high, then the interface is a single-port utopia-compliant interface controlled by the port 0 control registers. octet/cell handshake flag threshold txfull~/txclav look-ahead 0 x full after 4 more octets 1 00 (two-cell look-ahead) full after current cell + 2 cells 1 01 (single cell look- ahead) full after current cell + cell 1 10 or 11 (normal mode) full after current cell
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.3 configuration control registers 100046c conexant 3-13 use the following steps to initialize the cn8223 for proper utopia port operation: 1. put rs8234 in the global reset: write 0x40000000 to config0. 2. write rs8234 ? s config0 to appropriate values, but do not overwrite the global_reset bit. 3. put cn8223 in the reset mode: write 0x0080 to config_5. 4. initialize cn8223, including utopia interface if needed. 5. release cn8223 reset: write 0x0000 to config_5. 6. release rs8234 reset: set global_reset bit to 0. 7. enable rs8234 ? s reassembly coprocessor. 8. enable cn8223 ? s receiver: write 0x0c02 to cell_val register. 9. enable rs8234 ? s segmentation coprocessor. 0x2c ? utopia_2 (utopia port control register 2) the utopia_2 register is located at address 0x2c and controls operation of the utopia interface. bit field size name description 15 ? 6 10 reserved set to 0. 5 ? 0 6 reserved set to 35 hex.
3.0 registers cn8223 3.4 transmit control registers atm transmitter/receiver with utopia interface 3-14 conexant 100046c 3.4 transmit control registers 0x03 ? txfeac_errpat (transmit feac/error pattern register) the txfeac_errpat register is located at address 0x03. the eight msbs control the feac channel used for ds3. programming of the feac channel is discussed in section 2.8 . the eight lsbs of this register insert bip-8 errors in the transmitted plcp, g.832, or sonet overhead or hec errors in the cell header for end-to-end testing. the error pattern is xor ? ed with the selected field that is to be errored. bit field size name description 15 ? 10 6 transmit feac data six bits of serial data. 9 1 enable feac transmission enables feac transmission; message is transmitted 10 times. interrupt on dl_int when done. 8 1 enable receive feac interrupt turns on the interrupt for the feac receive. 7 ? 0 8 error insertion pattern bip-8 errors for plcp, g.832, or sonet.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.4 transmit control registers 100046c conexant 3-15 0x60 ? dl_ctrl_stat (hdlc data link control and status register) the dl_ctrl_stat register is located at address 0x60. the eight lsbs of this register are control bits and can be read or written. the eight msbs are status bits and can only be read. programming of the hdlc data link is discussed in section 2.8 . bit field size name description 15 1 receiver interrupt indicates that the receiver needs service. a read to dl_ctrl_stat clears this interrupt. 14 1 transmitter interrupt indicates that the transmitter needs service. a write to dl_ctrl_stat clears this interrupt. 13 ? 11 3 rx bytes[2:0] a 3-bit pointer to the last location written in the receive message buffer by the data link receiver. 10 1 idle code received indicates that an idle flag sequence (0111 1110) was received on the receive data link. 9 1 bad fcs set when an erroneous frame check sequence (fcs) was received at the end of a message or an idle flag is received that is not byte aligned. 8 1 abort flag received set if an abort sequence (seven consecutive 1s) was received on the receive data link. 7 1 enable receive data link interrupt enables the receiver interrupt to appear on the dl_int output pin. 6 1 disable data link transmission forces the data link bits to all 1s. 5 ? 3 3 tx bytes[2:0] a 3-bit pointer to the transmit message buffer indicating the location of the last byte to be transmitted. 2 1 abort message causes the data link transmitter to halt the message in progress, send an abort flag, and then resume transmission of idle flags on the data link. 1 1 send fcs controls the transmission of the fcs at the end of a message block. 0 1 send message instructs the transmitter to begin transmission of a message block on the data link. setting this bit removes the data link from idle flag transmission mode and enables transmitter interrupts to the controller for data bytes.
3.0 registers cn8223 3.4 transmit control registers atm transmitter/receiver with utopia interface 3-16 conexant 100046c 0x04 ? 0x07 ? cell_gen_x (cell generation control registers) the cell_gen_x registers are located at addresses 0x04 ? 0x07. each of the four fifo ports has its own atm cell generation control register, so x is 0, 1, 2 or 3. cell generation is described in detail in section 2.6 . a description of cell_gen_x control register addresses is provided in table 3-7 . table 3-7. cell_gen_x control register addresses address register name description 0x04 cell_gen_0 cell generation control ? port 0 + utopia 0x05 cell_gen_1 cell generation control ? port 1 0x06 cell_gen_2 cell generation control ? port 2 0x07 cell_gen_3 cell generation control ? port 3 bit field size name description 15, 14 2 reserved set to 0. 13 1 inhibit single cell generation inhibits cell transmission from the port for a single cell period and inserts an idle cell in its place. 12 1 error payload crc forces an error in the payload crc-10 field. a single error is generated; then this bit is cleared. 11 1 error hec forces an error in the atm header hec field. a single error is generated; then this bit is cleared. 10 1 disable payload crc disables payload crc-10 field generation and allows the existing field from the fifo input to pass. 9 1 disable hec disables the atm header hec field (octet 5) generation and allows the existing field from the fifo input to pass. the error mask in the txfeac_errpat register controls which bits are errored in the hec field by xor ? ing this mask with the calculated hec, allowing the microprocessor to generate a specific number of errors. 8 1 insert clp performs the same insertion function as insert gfc (bit 4) for the clp bit. 7 1 insert pt performs the same insertion function as insert gfc (bit 4) for the 3-bit payload type field. 6 1 insert vci performs the same insertion function as insert gfc (bit 4) for the 16-bit vci field. 5 1 insert vpi performs the same function as the insert gfc (bit 4) for the 8-bit vpi field. 4 1 insert gfc allows the 4-bit gfc field obtained from the fifo interface to be overwritten with the value programmed in the corresponding tx_hdr registers [0x0c ? 0x13]. this bit is only valid in 52-, 53-, and 57-octet modes. in 48-octet mode, the gfc field is always taken from the tx_hdr register. 3, 2 2 port priority allows the cell generator to assign four priority levels to the transmit source. 1, 0 2 cell generation mode selects the mode of operation for the generation circuit. 0 0 48 octet 0 1 52 octet 1 0 53 octet 1 1 57 octet
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.4 transmit control registers 100046c conexant 3-17 0x08 ? tx_rate_23 (transmit rate control register) the tx_rate_23 register is located at address 0x08. each 8-bit field controls the maximum transmission rate for ports 3 or 2. these fields are used to control the percentage of the total line rate allocated to each of the four fifo transmit ports. setting these fields to 0 stops transmission on the port. setting to 0xff allows the maximum available rate. transmit rate control is described in section 2.7.3 . 0x09 ? tx_rate_01 (transmit rate control register) the tx_rate_01 register is located at address 0x09. each 8-bit field controls the maximum transmission rate for ports 1 or 0. these fields are used to control the percentage of the total line rate allocated to each of the four fifo transmit ports. setting these fields to 0 stops transmission on the port. setting to 0xff allows the maximum available rate. transmit rate control is described in section 2.7.3 . 0x0a ? tx_idle_12 (transmit idle header register) the tx_idle_12 register is located at address 0x0a. this register sets the atm idle cell header octets 1 and 2. 0x0b ? tx_idle_34 (transmit idle header register) the tx_idle_34 register is located at address 0x0b. this register sets the atm idle cell header octets 3 and 4. bit field size name description 15 ? 8 8 rate value-port 3 maximum rate: 0x00 to 0xff 7 ? 0 8 rate value-port 2 maximum rate: 0x00 to 0xff bit field size name description 15 ? 8 8 rate value-port 1 maximum rate: 0x00 to 0xff 7 ? 0 8 rate value-port 0 maximum rate: 0x00 to 0xff bit field size name description 15 ? 8 8 header octet 1 normally written to 00. 7 ? 0 8 header octet 2 normally written to 00. bit field size name description 15 ? 8 8 header octet 3 normally written to 00. 7 ? 0 8 header octet 4 normally written to 01.
3.0 registers cn8223 3.4 transmit control registers atm transmitter/receiver with utopia interface 3-18 conexant 100046c 0x2a ? idle_pay (transmit idle cell payload register) the idle_pay register is located at address 0x2a. this register sets the atm idle cell payload contents. 0x0c ? 0x13 ? tx_hdrx_12, tx_hdrx_34 (transmit header registers) the transmit header registers for port x (where x can be 0 to 3) are located at addresses 0x0c ? 0x13. these registers control the header value that is inserted in cells that are transmitted from port x. cell generation is described in detail in section 2.6 . table 3-8 defines the tx_hdrx register addresses. bit field size name description 15 ? 9 7 reserved set to 0. 8 1 enable idle cell crc insertion allows the crc-10 value to be calculated and inserted into the last 10 bits of each transmitted idle cell. normally written to 0. 7 ? 0 8 idle cell payload octet inserted into each of the 48 octets of the information field in all idle cells transmitted. normally written to 6a. table 3-8. tx_hdrx register addresses address register name description 0x0c tx_hdr0_12 transmit port 0 atm header value - octets 1, 2 0x0d tx_hdr0_34 transmit port 0 atm header value - octets 3, 4 0x0e tx_hdr1_12 transmit port 1 atm header value - octets 1, 2 0x0f tx_hdr1_34 transmit port 1 atm header value - octets 3, 4 0x10 tx_hdr2_12 transmit port 2 atm header value - octets 1, 2 0x11 tx_hdr2_34 transmit port 2 atm header value - octets 3, 4 0x12 tx_hdr3_12 transmit port 3 atm header value - octets 1, 2 0x13 tx_hdr3_34 transmit port 3 atm header value - octets 3, 4 bit field size name description 15 ? 88 header value ? octet 1 transmit port x atm header value ? octet 1 7 ? 08 header value ? octet 2 transmit port x atm header value ? octet 2 bit field size name description 15 ? 88 header value ? octet 3 transmit port x atm header value ? octet 3 7 ? 08 header value ? octet 4 transmit port x atm header value ? octet 4
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.5 receive control registers 100046c conexant 3-19 3.5 receive control registers 0x14 ? cell_val (cell validation control register) the cell_val register is located at address 0x14. validation checks performed by the validation process can be individually disabled with the ? disable ? control bits. these disable bits are global disables for all ports. port disables for payload length and payload crc checks can also be found in config_4. bit field size name description 15 1 start-of-cell/write error output selects the function of the fctrl_out[10] pin. when this bit is low, the output indicates a fifo write error. when this bit is high, the output is a start-of-cell marker for the received cell data on the fifo data port. 14 1 disable cell receiver disables all cell validation and output after physical layer reception. this disable control is internally synchronized to take effect on cell boundaries. 13 1 enable status octet enables status output in 53-octet mode on port 3. see section 2.6 , for additional information. when this bit is high, the hec octet position in the fifo output data is omitted and a status word is appended to the end of the cell as octet number 53. in 53-octet cell formats, if status output is enabled with this bit, none of the other ports should be programmed for 53-octet output. 12 1 header only output enables a 5-octet output mode on port 3 only. see section 2.6 , for additional information. only the 4 header octets of cells addressed to port 3 and the status octet are output to the fifo port. in 53-octet cell formats, if status output is enabled with this bit, none of the other ports should be programmed for 53-octet output. 11 1 disable payload crc disables the payload crc check. this disable controls only the output of cells to the fifo interface and does not control the counting of payload crc errors. (this applies for all ports.) 10 1 disable payload len disables the payload length check. this disable controls only the output of cells to the fifo interface and does not control the counting of payload length errors. (this applies for all ports.) 9 1 disable hec check disables the check of the header error control octet. the cn8223 will pass cells with hec errors if this bit is set to 1. this bit is not functional in utopia mode. 81enable hec correction enables the hec correction mode for single-bit header errors. if this bit is set to 0, then no correction is performed but error detection is always performed. error correction must be disabled if hec coverage is set for smds/802.6 mode or if enable hec coset (bit 0) in config_3 is not enabled. 7 ? 6 2 cell output mode-port 3 number of atm cell octets delivered to the fifo interface. 00 - 48 octets: payload only mode 01 - 52 octets: header + payload, no hec 10 - 53 octets: header + hec + payload 11 - 57 octets: plcp mode for all table entries
3.0 registers cn8223 3.5 receive control registers atm transmitter/receiver with utopia interface 3-20 conexant 100046c 5 ? 4 2 cell output mode-port 2 number of atm cell octets delivered to the fifo interface. 00 - 48 octets: payload only mode 01 - 52 octets: header + payload, no hec 10 - 53 octets: header + hec + payload 11 - 57 octets: plcp mode 3 ? 2 2 cell output mode-port 1 number of atm cell octets delivered to the fifo interface. 00 - 48 octets: payload only mode 01 - 52 octets: header + payload, no hec 10 - 53 octets: header + hec + payload 11 - 57 octets: plcp mode 1, 0 2 cell output mode-port 0 number of atm cell octets delivered to the fifo interface. 00 - 48 octets: payload only mode 01 - 52 octets: header + payload, no hec 10 - 53 octets: header + hec + payload 11 - 57 octets: plcp mode bit field size name description
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.5 receive control registers 100046c conexant 3-21 0x15 ? 0x1c ? hdr_valx_12, hdr_valx_34 (receive header value register) the receive header value registers for port x (where x can be 0 to 3) are located at addresses 0x15 ? 0x1c. the header values direct atm cells to each port. if an incoming atm cell header matches the value in the header register, the cell is directed to that port. receive header mask registers further qualify atm cell reception. table 3-9 defines the hdr_valx register addresses. table 3-9. hdr_valx register addresses address register name description 0x15 hdr_val0_12 receive port 0 atm header value ? octets 1, 2 0x16 hdr_val0_34 receive port 0 atm header value ? octets 3, 4 0x17 hdr_val1_12 receive port 1 atm header value ? octets 1, 2 0x18 hdr_val1_34 receive port 1 atm header value ? octets 3, 4 0x19 hdr_val2_12 receive port 2 atm header value ? octets 1, 2 0x1a hdr_val2_34 receive port 2 atm header value ? octets 3, 4 0x1b hdr_val3_12 receive port 3 atm header value ? octets 1, 2 0x1c hdr_val3_34 receive port 3 atm header value ? octets 3, 4 hdr_val0_12, hdr_val1_12, hdr_val2_12, hdr_val3_12 bit field size name description 15 ? 88header value ? octet 1 receive port x atm header match value ? octet 1 7 ? 08header value ? octet 2 receive port x atm header match value ? octet 2 hdr_val0_34, hdr_val1_34, hdr_val2_34, hdr_val3_34 bit field size name description 15 ? 88 header value ? octet 3 receive port x atm header match value ? octet 3 7 ? 08 header value ? octet 4 receive port x atm header match value ? octet 4
3.0 registers cn8223 3.5 receive control registers atm transmitter/receiver with utopia interface 3-22 conexant 100046c 0x1d ? 0x24 ? hdr_mskx_12, hdr_mskx_34 (receive header mask register) the receive header mask registers for port x (where x can be 0 to 3) are located at addresses 0x1d ? 0x24. these registers modify the atm cell screen in the receive header value register. setting a bit in the mask register causes the corresponding bit in the received atm cell header to be disregarded for screening. for example, setting hdr_msk0_12, bit 0 to 1 causes atm cells to be accepted to port 0 with either 1 or 0 in the octet 1, bit 0 position. combinations of receive header mask bits can select groups of atm vpi/vcis for each of the four ports. the same cells can be sent to more than one port. setting all bits to 1s overrides the contents of the receive header value register. hdr_mskx register addresses are listed in table 3-10 . table 3-10. hdr_mskx register addresses address register name description 0x1d hdr_msk0_12 receive port 0 atm header mask ? octets 1, 2 0x1e hdr_msk0_34 receive port 0 atm header mask ? octets 3, 4 0x1f hdr_msk1_12 receive port 1 atm header mask ? octets 1, 2 0x20 hdr_msk1_34 receive port 1 atm header mask ? octets 3, 4 0x21 hdr_msk2_12 receive port 2 atm header mask ? octets 1, 2 0x22 hdr_msk2_34 receive port 2 atm header mask ? octets 3, 4 0x23 hdr_msk3_12 receive port 3 atm header mask ? octets 1, 2 0x24 hdr_msk3_34 receive port 3 atm header mask ? octets 3, 4 bit field size name description 15 ? 8 8 header value ? octet 1 receive port x atm header mask value ? octet 1 7 ? 0 8 header value ? octet 2 receive port x atm header mask value ? octet 2 hdr_val0_34, hdr_val1_34, hdr_val2_34, hdr_val3_34 bit field size name description 15 ? 88header value ? octet 3 receive port x atm header mask value ? octet 3 7 ? 08header value ? octet 4 receive port x atm header mask value ? octet 4
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.5 receive control registers 100046c conexant 3-23 0x25, 0x26 ? rx_idle_12, rx_idle_34 (receive idle header registers) the receive idle header value registers are located at addresses 0x25 and 0x26. these registers define atm idle cells for the cell receiver. idle cells are counted and usually discarded. 0x27, 0x28 ? idle_msk_12, idle_msk_34 (receive idle header mask register) the receive idle header mask registers are located at addresses 0x27 and 0x28. these registers modify the atm cell screen in the rx_idle_12, 34 registers. setting a bit in the mask register causes the corresponding bit in the received atm idle cell header to be disregarded for screening. for example, setting idle_msk_12, bit 0 to 1, causes cells to be accepted as atm idle cells with either 1 or 0 in the octet 2, bit 0 position. bit field size name description 15 ? 88header value ? octet 1 receive port x atm header match value ? octet 1 7 ? 08header value ? octet 2 receive port x atm header match value ? octet 2 bit field size name description 15 ? 88header value ? octet 3 receive port x atm header match value ? octet 3 7 ? 08header value ? octet 4 receive port x atm header match value ? octet 4 bit field size name description 15 ? 8 8 header value ? octet 1 receive atm idle cell header mask value ? octet 1 7 ? 0 8 header value ? octet 2 receive atm idle cell header mask valu ? octet 2 bit field size name description 15 ? 8 8 header value ? octet 3 receive atm idle cell header mask value ? octet 3 7 ? 0 8 header value ? octet 4 receive atm idle cell header mask value ? octet 4
3.0 registers cn8223 3.6 interrupt enable control registers atm transmitter/receiver with utopia interface 3-24 conexant 100046c 3.6 interrupt enable control registers four registers enable interrupts to appear on the stat_int interrupt output pin (pin 64). the en_line_int (0x2d), en_event_int (0x2e), en_ovfl_int (0x2f), and en_cell_int (0x30) enable interrupts based on the same bit positions in the corresponding status registers. for example, the en_line_int register enables the interrupts reported in the line_status register. 0x2d ? en_line_int (enable line interrupts) the en_line_int register is located at address 0x2d and enables interrupts for the line_status register (0x38). setting a bit in en_line_int enables each interrupt condition to appear on stat_int. bit ext. framer (57 octet) internal ds3 internal g.751 e3 sts-1/sts-3c/ stm-1 g.832 e3/e4 15 0 0 0 line febe error 0 14 one second count one second count one second count one second count one second count 13 invalid febe invalid febe invalid febe signal label mismatch payload type mismatch 12 febe all-1s febe all-1s febe all-1s path ferf error ma ferf 11 plcp febe error plcp febe error plcp febe error path febe error ma febe 10 plcp bip error plcp bip error plcp bip error summary bip error em bip error 9 plcp frame error plcp frame error plcp frame error line ferf x 8 plcp yellow plcp yellow/loc plcp yellow loc loc 7plcp lof 2 ? 3plcp lof 2 ? 3plcp lof 2 ? 3 sts lof 2 ? 3 e3/e4 lof 2 ? 3 6 plcp lof plcp lof plcp lof sts lof e3/e4 lof 5 plcp oof plcp oof/loc plcp oof sts oof e3/e4 oof 4 x ds3 x bit yellow e3 a bit yellow path yellow x 3 x ds3 idle code x path ais x 2 x ds3 ais e3 ais line ais e3/e4 ais 1 x ds3 oof e3 oof sts lop x 0 los (input) los (input) los (input) los (input) los (input) note(s): notes: 1. en_line_int and line_status have definitions that change with line interface mode. 2. ? x ? means content should be disregarded.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.6 interrupt enable control registers 100046c conexant 3-25 0x2e ? en_event_int (enable event interrupts) the en_event_int register is located at address 0x2e and enables interrupts for the event_status register (0x39). setting a bit in en_event_int enables each interrupt condition to appear on stat_int. bit field size name description 15 1 receiver hold input interrupt enable indicates that an active-high input was received on the rcv_hld input pin. 14 ? 13 4 reserved set to 0. 12 1 aps interrupt enables interrupt when received value of the k1 or k2 byte changes in the sonet frame. 11 1 start of cell error indicates that a start of cell alignment error was received on the fctrl_in[0] input pin (109). 10 1 port 3 input parity error interrupt enable enables parity error interrupt from fifo data input port 3. these interrupts and status bits will be active only if input parity checking is enabled in config_3. 9 1 port 2 input parity error interrupt enable enables parity error interrupt from fifo data input port 2. these interrupts and status bits will be active only if input parity checking is enabled in config_3. 8 1 port 1 input parity error interrupt enable enables parity error interrupt from fifo data input port 1. these interrupts and status bits will be active only if input parity checking is enabled in config_3. 7 1 port 0 input parity error interrupt enable enables parity error interrupt from fifo data input port 0. these interrupts and status bits will be active only if input parity checking is enabled in config_3. 6 1 idle cells interrupt enable enables interrupt when header of an incoming cell matches the header value programmed in the rx_idle and idle_msk registers. 5 1 non-matching cells interrupt enable enables interrupt when the header of an incoming cell does not match any of the header values programmed in the hdr_valx and hdr_mskx registers. 4 1 non-zero gfc interrupt enable enables interrupt when the 4-bit gfc field of an incoming cell header is any value other than 0000. 3 1 payload length error interrupt enable enables interrupt when an error is detected in the 6-bit payload length field of the cell trailer. this event is meaningful only for aal3/4 payloads that contain a payload length. 2 1 payload crc error interrupt enable enables interrupt when an error is detected in the 10-bit payload crc of the cell trailer. this event is meaningful only for aal3/4 payloads that contain a payload crc. 1 1 hec error not corrected interrupt enable enables interrupt when an uncorrectable error is detected in the hec octet of the cell header. 0 1 hec error corrected interrupt enable enables interrupt when an error is detected and corrected in the hec octet of the cell header.
3.0 registers cn8223 3.6 interrupt enable control registers atm transmitter/receiver with utopia interface 3-26 conexant 100046c 0x2f ? en_ovfl_int (enable overflow interrupts) the en_ovfl_int register is located at address 0x2f and enables interrupts for the ovfl_status register (0x3a). setting a bit in en_ovfl_int enables each interrupt condition to appear on stat_int. bit field size name description 15 1 counter 9 line/phy counter interrupt enable enables interrupts when line/phy error counter 9 overflows. 14 1 counter 8 line/phy counter interrupt enable enables interrupts when line/phy error counter 8 overflows. 13 1 counter 7 line/phy counter interrupt enable enables interrupts when line/phy error counter 7 overflows. 12 1 counter 6 line/phy counter interrupt enable enables interrupts when line/phy error counter 6 overflows. 11 1 counter 5 line/phy counter interrupt enable enables interrupts when line/phy error counter 5 overflows. 10 1 counter 4 line/phy counter interrupt enable enables interrupts when line/phy error counter 4 overflows. 9 1 counter 3 line/phy counter interrupt enable enables interrupts when line/phy error counter 3 overflows. 8 1 counter 2 line/phy counter interrupt enable enables interrupts when line/phy error counter 2 overflows. 7 1 counter 1 line/phy counter interrupt enable enables interrupts when line/phy error counter 1 overflows. 6 1 idle cell interrupt enable enables interrupts when the idle_cell_cnt counter overflows. 5 1 non-matching cell interrupt enable enables interrupts when the non_match_cnt counter overflows. 4 1 non-zero gfc interrupt enable enables interrupts when the non_zero_gfc counter overflows. 3 1 payload length error interrupt enable enables interrupts when the pay_len_err counter overflows. 2 1 payload crc error interrupt enable enables interrupts when the pay_crc_err counter overflows. 1 1 hec error not corrected interrupt enable enables interrupts when the uncor_hec_err counter overflows. 0 1 hec error corrected interrupt enable enables interrupts when the cor_hec_err counter overflows.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.6 interrupt enable control registers 100046c conexant 3-27 0x30 ? en_cell_int (enable cell interrupts) the en_cell_int register (0x30) enables interrupts for the cell_status register (0x3b). setting a bit in en_cell_int enables each interrupt condition to appear on stat_int (pin 64). 0x32 ? tx_k1k2 (transmit k1 and k2 value) the tx_k1k2 register (0x32) contains the aps transmit k1 and k2 values. 0x33 ? rx_k1k2 (receive k1 and k2 value) the rs_k1k2 register (0x33) contains the aps receive k1 and k2 values. bit field size name description 15 1 cell sent cntr ovfl ? port 3 enables an interrupt if the cell_sent_cnt3 counter overflows. 14 1 cell sent cntr ovfl ? port 2 enables an interrupt if the cell_sent_cnt2 counter overflows. 13 1 cell sent cntr ovfl ? port 1 enables an interrupt if the cell_sent_cnt1 counter overflows. 12 1 cell sent cntr ovfl ? port 0 enables an interrupt if the cell_sent_cnt0 counter overflows. 11 1 cell rcvd cntr ovfl-port 3 enables an interrupt if the cell_rcv_cnt3 counter overflows. 10 1 cell rcvd cntr ovfl-port 2 enables an interrupt if the cell_rcv_cnt2 counter overflows. 9 1 cell rcvd cntr ovfl-port 1 enable an interrupt if the cell_rcv_cnt1 counter overflows. 8 1 cell rcvd cntr ovfl-port 0 enables an interrupt if the cell_rcv_cnt0 counter overflows. 71cell rcvd ? port 3 enables port 3 header match interrupt. 61cell rcvd ? port 2 enables port 2 header match interrupt. 51cell rcvd ? port 1 enables port 1 header match interrupt. 41cell rcvd ? port 0 enables port 0 header match interrupt. 3 1 cell sent ? port 3 enables an interrupt when a cell is transmitted from port 3. 2 1 cell sent ? port 2 enables an interrupt when a cell is transmitted from port 2. 1 1 cell sent ? port 1 enables an interrupt when a cell is transmitted from port 1. 0 1 cell sent ? port 0 enables an interrupt when a cell is transmitted from port 0. bit field size name description 15-8 8 tx_k1 value to transmit in the k1 byte of the sonet frame. 7-0 8 tx_k2 value to transmit in the k2 byte of the sonet frame. bit field size name description 15-8 8 rx_k1 value of the last k1 byte received in the sonet frame. a change in this value causes bit 12 of the event_status register to be set. 7-0 8 rx_k2 value of the last k2 byte received in the sonet frame. a change in this value causes bit 12 of the event_status register to be set.
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-28 conexant 100046c 3.7 status register overview there are four status registers, as defined in table 3-11 . status registers are read-only. some of the status registers will be cleared when read, or have separate clear functions. the status indications can interrupt the microprocessor if the corresponding bit is set in an interrupt enable control register ( section 3.6 ). the interrupt appears on the stat_int pin (pin 64). table 3-11. atm transmitter/receiver status registers, counters, and data link control address name function 0x38 line_status line framer/phy interrupt status 0x39 event_status event interrupt status ? all bits are event driven 0x3a ovfl_status counter overflow interrupt status ? all bits are event driven 0x3b cell_status cell counter interrupt status ? all bits are event driven 0x3c rxfeac_ver receive feac/part number/version number
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.7 status register overview 100046c conexant 3-29 0x38 ? line_status (line framer/phy interrupt status register) the line_status register is located at address 0x38. bit definitions for this register depend on the line interface mode selected. line_status indicates alarms, errors, and framing states of the cn8223 line receivers. for 53-octet formats that use external framers or the parallel input, the only meaningful bit is the loc indication (bit 8). line_status interrupts appear on stat_int, if they are enabled by writing the desired bits in en_line_int. line_status bits are set regardless of whether interrupts are enabled. each line_status bit is latched until read and then cleared if the condition is no longer present. if a status condition clears before the register is read, the status bit will still be held. current status can be obtained by reading the register twice in succession. upper and lower bytes of line_status operate differently in regard to interrupt generation. upper definitions of line_status (bits 15 ? 9) are events that generate an interrupt when the event occurs (for example, if line ferf [bit 9] in sts-3c mode occurs, a single interrupt will be generated when the line ferf occurs). the lower definitions of line_status (bits 8 ? 0) are level-sensitive conditions, meaning interrupts occur on any change of state. for example, when los occurs in sts-3c mode, an interrupt occurs. when los goes away, a second interrupt occurs. the contents of the line_status register are the logical or of the status event, for instance, oof and stat_int line. in sonet/sdh or g.832 e3/e4 modes, bits 9, 12, and 13 also become level-sensitive. two examples of this are given: example 1: if the line is disconnected, the oof interrupt goes active. reading the line_status register causes the stat_int line (pin 64) to go inactive. reading the line_status register again continues to show the oof condition that caused the interrupt. reconnecting the line causes another interrupt. reading the line_status register will cause the stat_int line to go inactive and show oof active. (oof will show active because the contents of line_status are the logical or of oof and the stat_int line. see waveform in figure 3-1 .) reading the line_status register again will show oof inactive. example 2: if the line is disconnected, oof will again go active. if you reconnect the line before the line_status register is read, the stat_int line will go active. reading the line_status register will show oof active and cause stat_int line to go inactive. reading line_status register again will show oof in the inactive state because the line was reconnected. table 3-12 lists sts-1, sts-3c, and stm-1 line_status bit definitions. figure 3-1. line_status and oof example oof contents of the line_status register stat_int line read line_status read line_status 8223_030
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-30 conexant 100046c table 3-12. sts-1,sts-3c, stm-1 line_status bit definitions bit name description 15 line febe error set if any valid non-0 febe value (values 1 ? 24) is detected in the m1 octet of the sts-1/sts-3c/stm-1 overhead. 14 one-second count set if the one-second timer input is detected. 13 signal label mismatch set if the received value in the c2 octet does not equal 0x13 for seven consecutive frames. 12 path ferf error set if a value of 9 is detected in the most significant nibble of the g1 octet of the sts-1/sts-3c/stm-1 overhead. 11 path febe error set if any valid non-0 febe value (values 1 ? 8) is detected in the most significant nibble of the g1 octet of the sts-1/sts-3c/stm-1 overhead. 10 summary bip error set if there is an error in any of the b1, b2, b3 bip-8, or bip-24 codes at the receiver. 9 line ferf set if the three lsbs of the k2 octet are set to ? 110 ? for five consecutive frames. 8 loc indicates that hec cell delineation has been lost. cell delineation is lost if seven consecutive hec errors occur at the current cell delineation position. 7 sts lof 2 ? 3 set if sts lof is high for three consecutive one-second latching signals (rising edge on oneseci). 6 sts lof set when sts oof is active for 24 consecutive sonet frames. 5 sts oof set if four consecutive errored a1/a2 framing patterns are observed. for sts-3c/stm-1, the pattern observed consists of the third a1 octet and the first a2 octet. 4 path yellow set if the path yellow bit in the g1 octet is set for 10 consecutive frames. the rdi qualifier for this alarm can be observed in bits 8 and 9 of the config_5 register. 3 path ais set if h1 and h2 octets are all 1s for three consecutive frames. 2 line ais set if the three lsbs of the k2 octet are set to ? 111 ? for five consecutive frames. 1 sts lop set if a valid pointer as defined in tr-nwt-000253 cannot be found in the h1/h2 pointer of the sts-1/sts-3c/stm-1 frame. 0 los (input) set if there is a los detected by the rxlos~ input pin. for sts-3c/stm-1, the only source of los is rxlos~. cells will continue to be output on the receive side until locd is detected, which is about 6 or 7 cells. to stop output of cells immediately, connect rxlos~ to rcv_hld after inverting.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.7 status register overview 100046c conexant 3-31 table 3-13 provides definitions for the ds3 plcp and direct mapping mode line_status bits. table 3-13. ds3 plcp and direct mapping mode line_status bit definitions bit name description 15 0 not used 14 one-second count set if the one-second timer input is detected. 13 plcp invalid febe set if an invalid febe is detected (9 ? f) in the g1 octet in 57-octet plcp formats. not used in direct mapping mode. 12 plcp febe all-1s set if an invalid febe = f is detected in the g1 octet in 57-octet plcp formats. not used in direct mapping mode. 11 plcp febe error set if any valid non-0 febe value (values 0x1 ? 0x8) is detected in the g1 octet in 57-octet plcp formats. not used in direct mapping mode. 10 plcp bip error set if there is an error in the bip-8 code (b1 octet) checking in 57-octet plcp formats. not used in direct mapping mode. 9 plcp frame error set if there is an error in either the a1 or a2 octets of the plcp frame pattern for 57-octet plcp formats. not used in direct mapping mode. 8 plcp yellow/loc in plcp mode, plcp yellow indicates that the yellow alarm bit in the g1 octet (57-octet modes) has been active for 10 consecutive plcp frames. this bit will also be active for 57-octet formats using external framers or the parallel interface. in direct mapping mode, loc indicates that hec cell delineation has been lost. cell delineation is lost if seven consecutive hec errors occur at the current cell delineation position.this bit will be active for 53-octet formats using external framers or the parallel interface. (this bit is functionally redundant with bit 5 when configured in this mode). 7plcp lof 2 ? 3 set if plcp lof is high for three consecutive one-second latching signals (rising edge on oneseci). not used in direct mapping mode. 6 plcp lof set when plcp oof is active for eight consecutive plcp frames. not used in direct mapping mode. 5 plcp oof/loc set if the plcp oof state has been entered for 57-octet plcp formats. in direct mapping mode, it indicates that hec cell delineation has been lost. cell delineation is lost if seven consecutive hec errors occur at the current cell delineation position. (this bit is functionally redundant with bit 8 when configured in direct mapping mode.) 4 ds3 x-bit yellow set if the internal ds3 framer detects both x1 and x2 low in an m-frame. 3 ds3 idle code indicates that the internal ds3 framer has detected an idle code signal. a ds3 idle code is a 1100... payload with valid framing and parity, equal x bits, and all subframe 3 c bits set to 0. 2 ds3 ais indicates that the internal ds3 framer has detected an ais. a ds3 ais is a 1010... payload with valid framing and parity, equal x bits, and all c bits set to 0. 1 ds3 oof indicates that the internal ds3 framer has lost frame alignment. an oof condition for ds3 occurs when 3 out of 16 f bits are in error, or 2 out of 3 m-frames contain m bit errors. reframe time is typically 1 ms. 0 los (input) set if there is a los detected by the internal b3zs/hdb3 decoder, or if the rxlos~ input pin is active low. internal los detection is the occurrence of 175 75 zeros prior to b3zs/hdb3 decoding. the rxlos~ input pin (rxin[4]) should be tied high unless an external line interface unit provides an active low los indication.
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-32 conexant 100046c table 3-14 lists definitions for e3 g.832 and e4 g.832 line_status bits. table 3-14. e3 g.832, e4 g.832 line_status bit definitions bit name description 15 0 not used 14 one-second count set if the one-second timer input is detected. 13 payload type mismatch set if the received value in the payload type bits of the ma octet do not equal 010 for seven consecutive frames. 12 ma ferf set if the ferf bit in the ma octet is high in the g.832 e3/e4 frame format. 11 ma febe set if the febe bit in the ma octet is high in the g.832 e3/e4 frame format. 10 em bip error set if there is an error in the bip-8 code (em octet) checking. 9xnot used 8 loc indicates that hec cell delineation has been lost. cell delineation is lost if seven consecutive hec errors occur at the current cell delineation position. this bit will also be active for 53-octet formats using external framers or the parallel interface. 7 e3/e4 lof 2 ? 3 set if e3/e4 lof is high for three consecutive one-second latching signals (rising edge on oneseci). 6 e3/e4 lof set when e3/e4 oof is active for 24 consecutive frames. 5 e3/e4 oof set if four consecutive errored a1/a2 framing patterns are observed in the g.832 e3/e4 format. 4, 3 x not used 2 e3/e4 ais set if an unframed all-1s pattern (less than 0.25% zero content) is detected in the g.832 e3/e4 format. 1xnot used 0 los (input) set if a los is detected by the internal b3zs/hdb3 decoder, or if the rxlos~ input pin is active low. internal los detection is the occurrence of 175 75 zeros prior to b3zs/hdb3 decoding. the rxlos~ input pin should be tied high unless an external line interface unit provides an active low los indication. note(s): ? x ? = bit position is undefined and should be ignored.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.7 status register overview 100046c conexant 3-33 table 3-15 lists definitions for e3 g.751 line_status bits. table 3-15. e3 g.751 line_status bit definitions bit g.751 e3 description 15 0 not used 14 one-second count set if the one-second timer input is detected. 13 invalid febe set if an invalid febe is detected (9 ? f). 12 febe all-1s set if an invalid febe = f is detected. 11 plcp febe error set if any valid non-0 febe value (values 0x1 ? 0x8) is detected in the g1 octet in 57-octet plcp formats 10 plcp bip error set if there is an error in the bip-8 code (b1 octet) checking in 57-octet plcp formats. 9 plcp frame error set if there is an error in either the a1 or a2 octets of the plcp frame pattern for 57-octet plcp formats. 8 plcp yellow plcp yellow indicates that the yellow alarm bit in the g1 octet (57-octet modes) has been active for 10 consecutive plcp frames. 7plcp lof 2 ? 3 set if plcp lof is high for three consecutive one-second latching signals (rising edge on oneseci). 6 plcp lof set when plcp oof is active for eight consecutive plcp frames. 5 plcp oof set if the plcp oof state has been entered for 57-octet plcp formats. 4 e3 a-bit yellow set if the internal e3 framer detects the a-bit high in a g.751 e3 frame. 3 x not used 2 e3 ais e3 alarm signal. indicates an unframed all-1s signal present for two consecutive frames. defined in itu recommendation g.775. 1 e3 oof out of frame. indicates four consecutive incorrect fas patterns. 0 los (input) set if there is a los detected by the internal b3zs/hdb3 decoder or if the rxlos~ input pin is active low. internal los detection is the occurrence of 175 75 zeros prior to b3zs/hdb3 decoding. the rxlos~ input pin should be tied high unless an external line interface unit provides an active low los indication. note(s): ? x ? = bit position is undefined and should be ignored.
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-34 conexant 100046c table 3-16 lists definitions for external framer, 57-octet mode, line_status bits. table 3-16. external framer, 57-octet mode, line_status bit definitions bit ext. framer (57 octet) description 15 0 not used 14 one second count set if the one-second timer input is detected. 13 invalid febe set if an invalid febe is detected (9 ? f). 12 febe all-1s set if an invalid febe = f is detected. 11 plcp febe error set if any valid non-0 febe value (values 0x1 ? 0x8) is detected in the g1 octet in 57-octet plcp formats 10 plcp bip error set if there is an error in the bip-8 code (b1 octet) checking in 57-octet plcp formats. 9 plcp frame error set if there is an error in either the a1 or a2 octets of the plcp frame pattern for 57-octet plcp formats. 8 plcp yellow plcp yellow indicates that the yellow alarm bit in the g1 octet (57-octet modes) has been active for 10 consecutive plcp frames. 7plcp lof 2 ? 3 set if plcp lof is high for three consecutive one-second latching signals (rising edge on oneseci). 6 plcp lof set when plcp oof is active for eight consecutive plcp frames. 5 plcp oof set if the plcp oof state has been entered for 57-octet plcp formats. 4 ? 1 x not used 0 los (input) set if there is a los detected by the internal b3zs/hdb3 decoder or if the rxlos~ input pin is active low. internal los detection is the occurrence of 175 75 zeros prior to b3zs/hdb3 decoding. the rxlos~ input pin should be tied high unless an external line interface unit provides an active low los indication. note(s): ? x ? = bit position is undefined and should be ignored.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.7 status register overview 100046c conexant 3-35 table 3-17 lists status indications for all modes. table 3-17. status indications for all modes bit sts-1/sts-3 c/stm-1 internal ds3 g.832 e3/e4 internal g.751 e3 ext. framer (57 octet) ext. framer (53 octet) 15 line febe error 00 0 00 14 one-sec. count one-second count one-second count one-second count one-second count one-second count 13 signal label mismatch invalid febe payload type mismatch invalid febe invalid febe invalid febe 12 path ferf error febe all 1s ma ferf febe all 1s febe all 1s febe all 1s 11 path febe error plcp febe error ma febe plcp febe error plcp febe error x 10 summary bip error plcp bip error em bip error plcp bip error plcp bip error x 9 line ferf plcp frame error x plcp frame error plcp frame error x 8 loc plcp yellow/loc loc plcp yellow plcp yellow loc 7 sts lof 2 ? 3plcp lof 2 ? 3 e3/e4 lof 2 ? 3 plcp lof 2 ? 3plcp lof 2 ? 3x 6 sts lof plcp lof e3/e4 lof plcp lof plcp lof x 5 sts oof plcp oof/loc e3/e4 oof plcp oof plcp oof loc 4 path yellow ds3 x-bit yellow x e3 a-bit yellow x x 3 path ais ds3 idle code x x x x 2 line ais ds3 ais e3/e4 ais e3 ais x x 1 sts lop ds3 oof x e3 oof x x 0 los (input) los (input) los (input) los (input) los (input) los (input) note(s): ? x ? = bit position is undefined and should be ignored.
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-36 conexant 100046c 0x39 ? event_status (event interrupt status register) the event_status register is located at address 0x39 and has receiver status conditions. bit field size name description 15 1 receiver hold input indicates that an active-high input was received on the rcv_hld input pin. 14 ? 13 2 reserved set to 0. 12 1 aps event set when the received value of the k1 or k2 byte changes in the sonet frame. 11 1 txutopia sync error this error indicates that the transmit utopia soc from the host interface is out of sync with the utopia fifo pointers. 10 1 fifo port 3 input parity error fifo port 3 parity error. this status bit and associated interrupt will be active only if input parity checking is enabled in config_3. 9 1 fifo port 2 input parity error fifo port 2 parity error. this status bit and associated interrupt will be active only if input parity checking is enabled in config_3. 8 1 fifo port 1 input parity error fifo port 1 parity error. this status bit and associated interrupt will be active only if input parity checking is enabled in config_3. 7 1 fifo port 0 input parity error fifo port 0 parity error. this status bit and associated interrupt will be active only if input parity checking is enabled in config_3. 6 1 idle cells set if the header of an incoming cell matches the header value programmed in the rx_idle and idle_msk registers. 5 1 non-matching cells set if the header of an incoming cell does not match any of the header values programmed in the hdr_valx and hdr_mskx registers. 4 1 non-zero gfc set if the 4-bit gfc field of an incoming cell header is any value other than 0000. 3 1 payload length error set if an error is detected in the 6-bit payload length field of the cell trailer. this event is meaningful only for aal3/4 payloads that contain a payload length. 2 1 payload crc error set if an error is detected in the 10-bit payload crc of the cell trailer. this event is meaningful only for aal3/4 payloads that contain a payload crc. 1 1 hec error-not corrected set if an uncorrectable error is detected in the hec octet of the cell header. 01hec error-corrected set if an error is detected and corrected in the hec octet of the cell header.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.7 status register overview 100046c conexant 3-37 0x3a ? ovfl_status (counter overflow interrupt status register) the ovfl_status register is located at address 0x3a and indicates when particular counters have overflowed. error and event counters are described in section 3.8 . bit field size name description 15 1 counter 9 line/phy set when line/phy error counter 9 overflows. 14 1 counter 8 line/phy set when line/phy error counter 8 overflows. 13 1 counter 7 line/phy set when line/phy error counter 7 overflows. 12 1 counter 6 line/phy set when line/phy error counter 6 overflows. 11 1 counter 5 line/phy set when line/phy error counter 5 overflows. 10 1 counter 4 line/phy set when line/phy error counter 4 overflows. 9 1 counter 3 line/phy set when line/phy error counter 3 overflows. 8 1 counter 2 line/phy set when line/phy error counter 2 overflows. 7 1 counter 1 line/phy set when line/phy error counter 1 overflows. 6 1 idle cell set when the idle_cell_cnt counter overflows. 5 1 non-matching cells set if the non_match_cnt counter overflows. 4 1 non-zero gfc set if the non_zero_gfc counter overflows. 3 1 payload length error set if the pay_len_err counter overflows. 2 1 payload crc set if the pay_crc_err counter overflows. 1 1 hec error ? not corrected set if the uncor_hec_err counter overflows. 0 1 hec error ? corrected set if the cor_hec_err counter overflows.
3.0 registers cn8223 3.7 status register overview atm transmitter/receiver with utopia interface 3-38 conexant 100046c 0x3b ? cell_status (interrupt status register) the cell_status register is located at address 0x3b. 0x3c ? rxfeac_ver (receive feac/part number/version number register) the rxfeac_ver register is located at address 0x3c. the lower 8 bits have fixed values. programming of the feac channel and use of these interrupts is discussed in section 2.8 . bit field size name description 15 1 cell sent cntr ovfl ? port 3 set if the cell_sent_cnt3 counter overflows. 14 1 cell sent cntr ovfl ? port 2 set if the cell_sent_cnt2 counter overflows. 13 1 cell sent cntr ovfl ? port 1 set if the cell_sent_cnt1 counter overflows. 12 1 cell sent cntr ovfl ? port 0 set if the cell_sent_cnt0 counter overflows. 11 1 cell rcvd cntr ovfl-port 3 set if the cell_rcv_cnt3 counter overflows. 10 1 cell rcvd cntr ovfl-port 2 set if the cell_rcv_cnt2 counter overflows. 9 1 cell rcvd cntr ovfl-port 1 set if the cell_rcv_cnt1 counter overflows. 8 1 cell rcvd cntr ovfl-port 0 set if the cell_rcv_cnt0 counter overflows. 7 1cell rcvd ? port 3 enables port 3 header match interrupt. 6 1cell rcvd ? port 2 enables port 2 header match interrupt. 5 1cell rcvd ? port 1 enables port 1 header match interrupt. 4 1cell rcvd ? port 0 enables port 0 header match interrupt. 3 1cell sent ? port 3 set when a cell is transmitted from port 3. 2 1cell sent ? port 2 set when a cell is transmitted from port 2. 1 1cell sent ? port 1 set when a cell is transmitted from port 1. 0 1cell sent ? port 0 set when a cell is transmitted from port 0. bit field size name description 15 ? 10 6 receive feac data contains the data received by the feac receiver. 9 1 receive feac interrupt indicates that the interrupt on the dl_int pin was from the feac receiver when the internal ds3 framer is enabled. 8 1 transmit feac interrupt indicates that the interrupt on the dl_int pin was from the feac transmitter when the internal ds3 framer is enabled. 7 ? 4 4 part number fixed value is e (1110). 3 ? 0 4 version number provides the version number of the part. cn8223 = 1 (0001)
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.8 event/error counters 100046c conexant 3-39 3.8 event/error counters the 24 counters to count line and interface events or errors are summarized in table 3-18 and explained in tables 3-20 through table 3-24 . the first nine (addresses 0x40 ? 0x48) provide counts of error events from the line or phy framers. the events that are counted depend on the mode of operation and are summarized in table 3-19 . the remaining counters provide counts of atm cell events. counters 5 ? 9 can be programmed to count block errors instead of individual errors for bip and febe status by setting count block errors (bit 11) in config_3. this provides support for g.826 performance monitoring. register summary cheat sheets are illustrated in figures 3-2 and 3-3 . table 3-18. line and interface events/errors counters address name function reference 0x40 line_phy_cntr 1 line framer/phy error counter 1 3.8 0x41 line_phy_cntr 2 line framer/phy error counter 2 3.8 0x42 line_phy_cntr 3 line framer/phy error counter 3 3.8 0x43 line_phy_cntr 4 line framer/phy error counter 4 3.8 0x44 line_phy_cntr 5 line framer/phy error counter 5 3.8 0x45 line_phy_cntr 6 line framer/phy error counter 6 3.8 0x46 line_phy_cntr 7 line framer/phy error counter 7 3.8 0x47 line_phy_cntr 8 line framer/phy error counter 8 3.8 0x48 line_phy_cntr 9 line framer/phy error counter 9 3.8 0x49 cor_hec_err count of corrected hec errors 2.6.2.3 0x4a uncor_hec_err count of uncorrected hec errors 2.6.2.3 0x4b pay_crc_err count of payload crc errors 2.6.2.3 0x4c pay_len_err count of payload length errors 2.6.2.3 0x4d non_zero_gfc count of non-zero gfc fields 2.6.2.3 0x4e cell_sent_cnt0 count of cells transmitted on port 0 2.6.1.1 0x4f cell_sent_cnt1 count of cells transmitted on port 1 2.6.1.1 0x50 cell_sent_cnt2 count of cells transmitted on port 2 2.6.1.1 0x51 cell_sent_cnt3 count of cells transmitted on port 3 2.6.1.1 0x52 cell_rcv_cnt0 count of cells received on port 0 2.6.2.3 0x53 cell_rcv_cnt1 count of cells received on port 1 2.6.2.3 0x54 cell_rcv_cnt2 count of cells received on port 2 2.6.2.3 0x55 cell_rcv_cnt3 count of cells received on port 3 2.6.2.3 0x56 idle_cell_cnt count of idle cells received on all ports 2.6.2.3 0x57 non_match_cnt count of active cells not matching any port vci/vpi 2.6.2.3
3.0 registers cn8223 3.8 event/error counters atm transmitter/receiver with utopia interface 3-40 conexant 100046c table 3-19. counted events cntr ext. framer (57 octet) internal ds3 internal g.751 e3 sts-1/sts-3c/stm-1 g.832 e3/e4 1 not used lcv lcv lcv lcv 2 not used frame errors frame errors sts oof events e3/e4 oof events 3 not used parity errors not used not used ma febe events 4 locd events (parallel interface) path parity errors not used locd events ma ferf events 5 not used ds3 febe errors not used b1 bip errors b1 bip errors 6 plcp frame error plcp frame error plcp frame error b2 bip errors not used 7 plcp oof events plcp oof events plcp oof events b3 bip errors locd events 8 plcp bip-8 errors plcp bip-8 errors plcp bip-8 errors path febe errors not used 9 plcp febe errors plcp febe errors plcp febe errors line febe errors not used
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.8 event/error counters 100046c conexant 3-41 table 3-20. internal sts-1, sts-3c event/error counters address counter name function 0x40 line_ phy_cntr_1 not used. 0x41 line_ phy_cntr_2 counts sts oof events. event also appears on line_status, bit 5. 0x42 line_ phy_cntr_3 not used. 0x43 line_ phy_cntr_4 counts loss of cell delineation (locd) events. event also appears on line_status, bit 8. 0x44 line_ phy_cntr_5 counts b1 bip-8 errors in sts-1, sts-3c, or stm-1. 0x45 line_ phy_cntr_6 counts b2 bip-8 errors in sts-1. bip-24 errors in sts-3c or stm-1. 0x46 line_ phy_cntr_7 counts b3 bip-8 errors in sts-1, sts-3c, or stm-1. 0x47 line_ phy_cntr_8 counts path febe errors in the g1 octet. event also appears on line_status, bit 11. 0x48 line_ phy_cntr_9 counts line febe errors in the z2 octet. event also appears on line_status, bit 15. 0x49 cor_hec_err counts corrected hec errors. event also appears on event_status, bit 0. 0x4a uncor_hec_err counts uncorrected hec errors. event also appears on event_status, bit 1. 0x4b pay_crc_err counts payload crc-10 errors, used in aal3/4. event also appears on event_status, bit 2. 0x4c pay_len_err counts payload length errors, used in aal3/4. event also appears on event_status, bit 3. 0x4d non_zero_gfc counts atm cells received with non-zero gfc fields. event also appears on event_status, bit 4. 0x4e cell_sent_cnt0 count of atm cells sent from fifo port 0. event also appears on cell_status, bit 0. 0x4f cell_sent_cnt1 count of atm cells sent from fifo port 1. event also appears on cell_status, bit 1. 0x50 cell_sent_cnt2 count of atm cells sent from fifo port 2. event also appears on cell_status, bit 2. 0x51 cell_sent_cnt3 count of atm cells sent from fifo port 3. event also appears on cell_status, bit 3. 0x52 cell_rcv_cnt0 count of atm cells received on fifo port 0. event also appears on cell_status, bit 4. 0x53 cell_rcv_cnt1 count of atm cells received on fifo port 1. event also appears on cell_status, bit 5. 0x54 cell_rcv_cnt2 count of atm cells received on fifo port 2. event also appears on cell_status, bit 6. 0x55 cell_rcv_cnt3 count of atm cells received on fifo port 3. event also appears on cell_status, bit 7. 0x56 idle_cell_cnt counts atm cells received that match the idle cell header screens. event also appears on event_status, bit 6. 0x57 non_match_cnt counts atm cells received that do not match any header screens. event also appears on event_status, bit 5.
3.0 registers cn8223 3.8 event/error counters atm transmitter/receiver with utopia interface 3-42 conexant 100046c table 3-21. internal ds3 plcp and direct mapping modes event/error counters address counter name function 0x40 line_ phy_cntr_1 line code violation (lcv) in b3zs/hdb3 decoder when enabled. for b3zs this counts both bipolar rule violations and occurrences of three or more 0s. for hdb3 this counts violations according to itu recommendation 0.161. 0x41 line_ phy_cntr_2 counts f and m-bit errors. 0x42 line_ phy_cntr_3 counts p1/p2 parity errors. 0x43 line_ phy_cntr_4 counts c bit path parity errors. 0x44 line_ phy_cntr_5 counts ds3 febe errors. 0x45 line_ phy_cntr_6 counts plcp frame errors if there is an error in either a1 or a2 octets. event also appears on line_status, bit 9. not used in direct mapping mode. 0x46 line_ phy_cntr_7 counts plcp oof events in plcp mode. counts locd events in direct mapping mode. event also appears on line_status, bit 5. not used in direct mapping mode. 0x47 line_ phy_cntr_8 counts plcp bip errors. event also appears on line_status, bit 10. not used in direct mapping mode. 0x48 line_ phy_cntr_9 counts plcp febe errors. event also appears on line_status, bit 11. not used in direct mapping mode. 0x49 cor_hec_err counts corrected hec errors. event also appears on event_status, bit 0. 0x4a uncor_hec_err counts uncorrected hec errors. event also appears on event_status, bit 1. 0x4b pay_crc_err counts payload crc-10 errors used in aal3/4. event also appears on event_status, bit 2. 0x4c pay_len_err counts payload length errors used in aal3/4. event also appears on event_status, bit 3. 0x4d non_zero_gfc counts atm cells received with non-zero gfc fields. event also appears on event_status, bit 4. 0x4e cell_sent_cnt0 count of atm cells sent from fifo port 0. event also appears on cell_status, bit 0. 0x4f cell_sent_cnt1 count of atm cells sent from fifo port 1. event also appears on cell_status, bit 1. 0x50 cell_sent_cnt2 count of atm cells sent from fifo port 2. event also appears on cell_status, bit 2. 0x51 cell_sent_cnt3 count of atm cells sent from fifo port 3. event also appears on cell_status, bit 3. 0x52 cell_rcv_cnt0 count of atm cells received on fifo port 0. event also appears on cell_status, bit 4. 0x53 cell_rcv_cnt1 count of atm cells received on fifo port 1. event also appears on cell_status, bit 5. 0x54 cell_rcv_cnt2 count of atm cells received on fifo port 2. event also appears on cell_status, bit 6. 0x55 cell_rcv_cnt3 count of atm cells received on fifo port 3. event also appears on cell_status, bit 7. 0x56 idle_cell_cnt counts atm cells received that match the idle cell header screens. event also appears on event_status, bit 6. 0x57 non_match_cnt counts atm cells received that do not match any header screens. event also appears on event_status, bit 5.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.8 event/error counters 100046c conexant 3-43 table 3-22. internal g.832 e3/e4 event/error counters address counter name function 0x40 line_ phy_cntr_1 line code violation in b3zs/hdb3 decoder when enabled. for b3zs this counts both bipolar rule violations and occurrences of three or more 0s. for hdb3 this counts violations according to itu recommendation 0.161. 0x41 line_phy_cntr_ 2 counts e3/e4 oof errors. event also appears on line_status, bit 5. 0x42 line_ phy_cntr_3 counts ma febe events. event also appears on line_status, bit 11. 0x43 line_ phy_cntr_4 counts ma ferf events. event also appears on line_status, bit 12. 0x44 line_ phy_cntr_5 counts em bip-8 errors. event also appears on line_status, bit 10. 0x45 line_ phy_cntr_6 not used. 0x46 line_ phy_cntr_7 counts locd events. event also appears on line_status, bit 8. 0x47 line_ phy_cntr_8 not used. 0x48 line_ phy_cntr_9 not used. 0x49 cor_hec_err counts corrected hec errors. event also appears on event_status, bit 0. 0x4a uncor_hec_err counts uncorrected hec errors. event also appears on event_status, bit 1. 0x4b pay_crc_err counts payload crc-10 errors, used in aal3/4. event also appears on event_status, bit 2. 0x4c pay_len_err counts payload length errors, used in aal3/4. event also appears on event_status, bit 3. 0x4d non_zero_gfc counts atm cells received with non-zero gfc fields. event also appears on event_status, bit 4. 0x4e cell_sent_cnt0 count of atm cells sent from fifo port 0. event also appears on cell_status, bit 0. 0x4f cell_sent_cnt1 count of atm cells sent from fifo port 1. event also appears on cell_status, bit 1. 0x50 cell_sent_cnt2 count of atm cells sent from fifo port 2. event also appears on cell_status, bit 2. 0x51 cell_sent_cnt3 count of atm cells sent from fifo port 3. event also appears on cell_status, bit 3. 0x52 cell_rcv_cnt0 count of atm cells received on fifo port 0. event also appears on cell_status, bit 4. 0x53 cell_rcv_cnt1 count of atm cells received on fifo port 1. event also appears on cell_status, bit 5. 0x54 cell_rcv_cnt2 count of atm cells received on fifo port 2. event also appears on cell_status, bit 6. 0x55 cell_rcv_cnt3 count of atm cells received on fifo port 3. event also appears on cell_status, bit 7. 0x56 idle_cell_cnt counts atm cells received that match the idle cell header screens. event also appears on event_status, bit 6. 0x57 non_match_cnt counts atm cells received that do not match any header screens. event also appears on event_status, bit 5.
3.0 registers cn8223 3.8 event/error counters atm transmitter/receiver with utopia interface 3-44 conexant 100046c table 3-23. internal g.751 e3 event/error counters address counter name function 0x40 line_ phy_cntr_1 line code violation in b3zs/hdb3 decoder when enabled. for b3zs this counts both bipolar rule violations and occurrences of three or more 0s. for hdb3 this counts violations according to itu recommendation 0.161. 0x41 line_ phy_cntr_2 counts errored fas patterns. 0x42 line_ phy_cntr_3 not used. 0x43 line_ phy_cntr_4 not used. 0x44 line_ phy_cntr_5 not used. 0x45 line_ phy_cntr_6 counts plcp frame errors if there is an error in either a1 or a2 octets. event also appears on line_status, bit 9. 0x46 line_ phy_cntr_7 counts plcp oof events. event also appears on line_status, bit 5. 0x47 line_ phy_cntr_8 counts plcp bip errors. event also appears on line_status, bit 10. 0x48 line_ phy_cntr_9 counts plcp febe errors. event also appears on line_status, bit 11. 0x49 cor_hec_err counts corrected hec errors. event also appears on event_status, bit 0. 0x4a uncor_hec_err counts uncorrected hec errors. event also appears on event_status, bit 1. 0x4b pay_crc_err counts payload crc-10 errors, used in aal3/4. event also appears on event_status, bit 2. 0x4c pay_len_err counts payload length errors, used in aal3/4. event also appears on event_status, bit 3. 0x4d non_zero_gfc counts atm cells received with non-zero gfc fields. event also appears on event_status, bit 4. 0x4e cell_sent_cnt0 number of atm cells sent from fifo port 0. 0x4f cell_sent_cnt1 number of atm cells sent from fifo port 1. 0x50 cell_sent_cnt2 number of atm cells sent from fifo port 2. 0x51 cell_sent_cnt3 number of atm cells sent from fifo port 3. 0x52 cell_rcv_cnt0 number of atm cells received on fifo port 0. 0x53 cell_rcv_cnt1 number of atm cells received on fifo port 1. 0x54 cell_rcv_cnt2 number of atm cells received on fifo port 2. 0x55 cell_rcv_cnt3 number of atm cells received on fifo port 3. 0x56 idle_cell_cnt counts atm cells received that match the idle cell header screens. event also appears on event_status, bit 6. 0x57 non_match_cnt counts atm cells received that do not match any header screens. event also appears on event_status, bit 5.
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.8 event/error counters 100046c conexant 3-45 table 3-24. external framer, 57-octet mode event/error counters address counter name function 0x40 line_ phy_cntr_1 not used. 0x41 line_ phy_cntr_2 not used. 0x42 line_ phy_cntr_3 not used. 0x43 line_ phy_cntr_4 locd events if parallel interface is used. 0x44 line_ phy_cntr_5 not used. 0x45 line_ phy_cntr_6 counts plcp frame errors if there is an error in either a1 or a2 octets. event also appears on line_status, bit 9. 0x46 line_ phy_cntr_7 counts plcp oof events. event also appears on line_status, bit 5. 0x47 line_ phy_cntr_8 counts plcp bip errors. event also appears on line_status, bit 10. 0x48 line_ phy_cntr_9 counts plcp febe errors. event also appears on line_status, bit 11. 0x49 cor_hec_err counts corrected hec errors. event also appears on event_status, bit 0. 0x4a uncor_hec_err counts uncorrected hec errors. event also appears on event_status, bit 1. 0x4b pay_crc_err counts payload crc-10 errors, used in aal3/4. event also appears on event_status, bit 2. 0x4c pay_len_err counts payload length errors, used in aal3/4. event also appears on event_status, bit 3. 0x4d non_zero_gfc counts atm cells received with non-zero gfc fields. event also appears on event_status, bit 4. 0x4e cell_sent_cnt0 number of atm cells sent from fifo port 0. 0x4f cell_sent_cnt1 number of atm cells sent from fifo port 1. 0x50 cell_sent_cnt2 number of atm cells sent from fifo port 2. 0x51 cell_sent_cnt3 number of atm cells sent from fifo port 3. 0x52 cell_rcv_cnt0 number of atm cells received on fifo port 0. 0x53 cell_rcv_cnt1 number of atm cells received on fifo port 1. 0x54 cell_rcv_cnt2 number of atm cells received on fifo port 2. 0x55 cell_rcv_cnt3 number of atm cells received on fifo port 3. 0x56 idle_cell_cnt counts atm cells received that match the idle cell header screens. event also appears on event_status, bit 6. 0x57 non_match_cnt counts atm cells received that do not match any header screens. event also appears on event_status, bit 5.
3.0 registers cn8223 3.8 event/error counters atm transmitter/receiver with utopia interface 3-46 conexant 100046c figure 3-2. register summary, cheat sheet 1 idle_pay (0x2a) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 idle cell payload octet enable idle cell crc insertion reserved txfeac_errpat (0x03) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 error insertion pattern enable receive feac interrupt transmit feac data enable feac transmission cell_gen_x (0x04?0x07) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 error payload crc disable payload crc insert clp insert pt port priority insert gfc insert vpi error hec disable hec reserved insert vci cell generation mode 1 0 0 0 48 octet 0 1 52 octet 1 0 53 octet 1 1 57 octet header and mask registers (0x15?0x1c, 0x1d?0x24) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 header octet 1 header octet 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 header octet 3 header octet 4 config_5 (0x31) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved hec ocd anomaly receive g1 bit 5 software reset transmit clock select enable external signal label transmit g1 bit 6 transmit g1 bit 5 integrate hec framing enable hdlc data link set g1 x bits all ones receive g1 bit 6 external 8-khz timing receiver hold enable enable parallel interface enable hec alignment enable cell scrambler enable one-second latching of line counters enable one-second latching of line status config_1 (0x00) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 sts-1 stuffing option source loopback phy type unframed input disable b3zs/hdb3 external framer disable locd config_2 (0x01) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 enable external overhead all-zeros febe overhead control transmit alarm control bip error insert all-ones febe config_3 (0x02) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 accept/reject header - port 3 accept/reject header - port 2 enable hec coset hec coverage enable ds1 prs generator disable write strobes on invalid cells check input parity parity odd/even force cycle stuffing/tx overhead control invert tx clock output accept/reject header - port 1 accept/reject header - port 0 count block errors reserved line loopback invert rx clock sampling config_4 (0x29) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 disable crc check - port 3 disable crc check - port 2 stm-1/sts-3c pointer enable external section trace delete idle cells enable taxi interface disable port reception - port 0 disable port reception - port 1 disable port reception - port 2 disable port reception - port 3 disable crc check - port 1 disable crc check - port 0 disable length check - port 3 disable length check - port 2 disable length check - port 1 disable length check - port 0 inhibit single cell generation 0 - ds1 1 - e1 2 - ds3 3 - 751 e3 4 - 804 e3 5 - e4 6 - sts1 7 - sts3 tx_rate registers (0x08, 0x09) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rate value - port 2 rate value - port 3 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 rate value - port 0 rate value - port 1 phy type 8223_031
cn8223 3.0 registers atm transmitter/receiver with utopia interface 3.8 event/error counters 100046c conexant 3-47 figure 3-3. register summary, cheat sheet 2 event_status (0x39) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receiver hold input reserved hec error - corrected hec error - not corrected payload crc error payload length error non-zero gfc non-matching cells idle cells input parity error - port 3 input parity error - port 2 input parity error - port 1 input parity error - port 0 rxfeac_ver (0x3c) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receive feac data receive feac interrupt version number part number transmit feac interrupt ovfl_status (0x3a) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 line/phy counter 9 line/phy counter 8 line/phy counter 7 line/phy counter 5 line/phy counter 3 line/phy counter 2 line/phy counter 6 line/phy counter 4 cell_status (0x3b) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 cell sent cntr ovfl - port 3 cell sent cntr ovfl - port 2 cell sent cntr ovfl - port 1 cell rcvd cntr ovfl - port 3 cell rcvd cntr ovfl - port 1 cell rcvd cntr ovfl - port 0 cell sent - port 0 cell sent - port 1 cell sent - port 2 cell sent - port 3 cell rcvd - port 0 cell rcvd - port 1 cell rcvd - port 2 cell rcvd - port 3 cell sent cntr ovfl - port 0 cell rcvd cntr ovfl - port 2 status octet 76 54 32 10 line/phy counter 1 hec error - corrected hec error - not corrected payload crc error payload length error non-zero gfc non-matching cells idle cells hec error - corrected hec error - not corrected payload length error payload crc error user data bit (aal5 eom) header match - port 0 header match - port 1 header match - port 2 rxbytes[2:0] idle code received dl_ctrl_stat (0x60) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 receiver interrupt transmitter interrupt bad fcs abort flag received send message send fcs abort message txbytes[2:0] disable data link transmission enable receive data link interrupt utopia_1 (0x2b) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved receive cut through threshold enable utopia interface octet/cell handshake flag threshold enable low latency mode reset rx fifo reset tx fifo utopia_2 (0x2c) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 reserved transmit cut through threshold bytes needed alarm threshold enable status octet header only output cell_val (0x14) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 disable cell receiver disable payload crc disable hec check enable hec correction cell output mode - port 1 cell output mode - port 2 cell output mode - port 3 disable payload length start-of-cell/write error output cell output mode - port 0 1 0 0 0 48 octet 0 1 52 octet 1 0 53 octet 1 1 57 octet aps interrupt start of cell 8223_032
3.0 registers cn8223 3.8 event/error counters atm transmitter/receiver with utopia interface 3-48 conexant 100046c
100046c conexant 4-1 4 4.0 electrical and mechanical specifications this chapter discusses the electrical specifications of the cn8223, such as power requirements, temperature ranges, dc characteristics and timing. a mechanical drawing is included. 4.1 power requirements and temperature range the cn8223 meets all specifications over a temperature range of ? 40 c to 85 c and input voltage range of 4.75 v to 5.25 v. the maximum current required for the circuit in operation is estimated at 300 ma (at 155 mhz). the thermal characteristics of the 160-pin pqfp are 51.9 c for ja (still air) and 37.1 c for ja (air flow 400 lfpm).
4.0 electrical and mechanical specifications cn8223 4.2 dc characteristics atm transmitter/receiver with utopia interface 4-2 conexant 100046c 4.2 dc characteristics all input and bidirectional pins have input thresholds compatible with cmos drive levels except those labeled as xxxhs. leakage current for each pin is less than 10 a in any state. this device should be handled as an esd-sensitive device. voltage on any signal pin that exceeds the power supply voltage by more than +0.5 v can induce destructive latchup. at v ol(max) = 0.4 v and v ol(min) = 2.4 v, all output and bidirectional pins have drive current i ol = 4 ma and i oh = ? 4 ma except for txout[0] and tclko, which are 8 ma drivers. the interrupt output pins are open drain and require external pull-up resistors. all output and bidirectional pins (except those labeled xxxhs) have cmos drive levels and can be used with cmos or ttl logic. the rxcki_hs, txcki_hs, and rxin_hs inputs are differential pecl level inputs for use in e4 and sts-3c/stm-1 modes. these inputs are automatically selected in these modes and have input thresholds of v dd ? 1.3 v. the pecl inputs should have v il = 3.4 v and v ih = 4.0 v. the txout_hs and tclko_hs outputs are differential pecl outputs for use in e4 and sts-3c/stm-1 modes. the ? hs ? outputs are active at all times and should be used (in e4 or sts-3c/stm-1 modes) in place of the txout[0] and tclko outputs, respectively. the ? non-hs ? outputs are automatically disabled in e4 or sts-3c/stm-1 modes to reduce switching noise injection into the ic. the switching threshold is at 3.7 v with a v ol(max) of 3.3 v (driver off with external resistor termination) and v oh(min) of 4.1 v (driver on). all timing measurements in the following tables are with 20 pf loading on the output pins.
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.2 dc characteristics 100046c conexant 4-3 table 4-1 defines the dc characteristics. table 4-1. dc characteristics symbol parameter conditions min typical max unit vt switching threshold cmos ttl ? 2.5 1.5 ? v vt+ schmitt trigger, positive-going threshold cmos ttl ? 1.77 2.0 2.0 2.25 v vt ? schmitt trigger, negative-going threshold cmos (5 v) ttl 1.0 0.8 1.5 1.04 ? v schmitt trigger input hysteresis voltage cmos vil to vih ttl vil to vih 1.0 0.4 1.5 0.8 ? v iin inputs vin = vdd ? 10 1 10 a inputs with pulldown resistors (5 v) vin = vdd 35 115 222 a inputs with pullup resistors (5 v) vin = vss ? 35 ? 115 ? 214 a voh voltage output high 4 ma outputs 8 ma outputs commercial /military ioh = ? 4 ma ioh = ? 8 ma 2.4 2.4 ?? v vol voltage output low 4 ma outputs 8 ma outputs commercial /military iol = ? 4 ma iol = ? 8 ma 2.4 2.4 ?? v idd quiescent supply current vin = vdd or vss user-design dependent vil voltage input low cmos levels ttl inputs ??? 0.2 vdd 0.8 vdd v vih voltage input high cmos levels ttl inputs ttl schmitt trigger inputs comm./ind./mil. temp range ind./mil. temp range 0.7 vdd 2.0 2.25 ?? v v v ios output short circuit current 4 ma outputs vdd = 5.25 v, vo = vdd vdd = 5.25 v, vo = vss vdd = 3.45 v, vo = vdd vdd = 3.45 v, vo = vss 37 ? 117 50 ? 99 90 ? 75 110 ? 60 140 ? 40 182 ? 31 ma ioz three-state output leakage current voh = vss or vdd ? 10 1 10 a cin input capacitance any input and bidirectional buffers 2.5 pf cout output capacitance ? 2.0 pf
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-4 conexant 100046c 4.3 timing this section includes timing diagrams and descriptions for the cn8223. 4.3.1 microprocessor interface timing table 4-2 and figure 4-1 display the timing requirements and characteristics of the microprocessor interface. all times are in nanoseconds. table 4-2. microprocessor interface timing name description min max t prclk processor clock period 30 2x cell rate t prh processor clock pulse width high 10 ? t prl processor clock pulse width low 10 ? t aspr address strobe setup to processor clock rising edge 4 ? t apr address setup to processor clock rising edge 1 ? t cspr chip select setup to processor clock rising edge 4 ? t csph chip select to processor clock rising edge hold time 8 ? t wpr write/read control setup to processor clock rising edge 1 ? t pras address strobe hold after processor clock rising edge t prh + 2 ns t prl ? 4 ns t dpr data setup to processor clock rising edge (write cycle) 1.0 ? t prd data hold after processor clock rising edge (write cycle) 3.0 ? t odd output enable low to data bus driven (read cycle) 1.5 6.0 t odv output enable low to data bus valid (read cycle) 1.6 6.0 t odi output enable high to data bus invalid (read cycle) 1.3 4.9 t odz output enable high to data bus high-z (read cycle) 1.4 5.1 t pdd prclk high to data bus driven (read cycle, oe~ low) 3.5 11.0 t pdv prclk high to data bus valid (read cycle, oe~ low) 3.6 11.0 t pdi prclk high to data bus invalid (read cycle, oe~ low) 3.2 10.0 t pdz prclk high to data bus high-z (read cycle, oe~ low) 3.2 10.0
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-5 figure 4-1. local processor interface timing prclk as ~ cs ~ a[7:1] w/r ~ d[15:0] hold t prh plus set up 4 ns min 2 ns min hold invalid 8 ns min set up 1 ns min hold 8 ns min hold 5 ns min hold 11 ns max invalid 4.9 ns max (t odi and t odz ) address latched in cn8223 valid vali d t prclk t prh t prl (t pdd and t pdv ) (t pdi and t pdz ) (t aspr and t cspr ) (t pras t ? 4 ns prl ) (t apr and t wpr ) (t csph ) oe ~ (t odd and t odv ) valid 6 ns. max hold 3.2 ns min (read operation) d[15:0] set up 1 ns min hold 3 ns min (write operation) valid (t prd ) (t dpr ) 8223_033
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-6 conexant 100046c 4.3.2 line interface timing tables 4-3 through 4-6 and figures 4-2 through 4-5 display the timing requirements and characteristics of the line interfaces and parallel data and overhead ports. all times are in nanoseconds. example liu circuits are provided in cn8223 evm schematics. table 4-3. line interface timing ? ds1, e1, ds3, e3 external framers name interval description min max t txcki 1 ? 7 transmit clock period (1) 22 ? t txh 1 ? 4 transmit clock pulse width high (2) 8.8 ? t tsck 3 ? 4 transmit sync setup to transmit clock falling edge 0 ? t ckts 4 ? 6 transmit sync hold after transmit clock falling edge 2.4 ? t ckd1 1 ? 2 transmit clock rising edge to ds1/e1 serial data out 2.9 12.2 t ckd2 4 ? 5 transmit clock falling edge to ds3/e3 serial data out 2.9 10.4 t rxcki 8 ? 13 receive clock period 22 ? t rxh 8 ? 11 receive clock pulse width high (2) 8.8 15 t rsck 9 ? 11 receive sync setup to receive clock falling edge 0 ? t ckrs 11 ? 12 receive sync hold after receive clock falling edge 3.4 ? t rdck 10 ? 11 receive data setup to receive clock falling edge 2.3 ? t ckdr 11 ? 14 receive data hold after receive clock falling edge 2.6 ? note(s): (1) nominal clock periods are: ds1 ? 648 ns e1 ? 488 ns e3 ? 29.1 ns ds3 ? 22.4 ns (2) duty cycle must be 40/60 at maximum input clock rate.
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-7 figure 4-2. line interface timing ? ds1, e1, ds3, e3 external framers txcki,txckihs txsyi txdato (ds1/e1) 10 14 912 13 11 8 5 2 3 6 7 4 1 txdato (ds3/e3) rxcki,rxckihs rxsyi rxdati 8223_034 table 4-4. line interface timing ? internal framers name interval description min max t txcki 1 ? 6 transmit clock period (1) 6.4 ? t txh 1 ? 5 transmit clock pulse width high (2) 2.9 ? t cico 1 ? 2 transmit clock in to clock out delay (non-inverted) 2.6 10.0 t cod 2 ? 3 transmit clock out to transmit data out 1.0 4.0 t copn 2 ? 4 transmit clock out to transmit pos/neg out 0.1 1.0 t rxcki 7 ? 11 receive clock period 6.4 ? t rxh 7 ? 10 receive clock pulse width high (2) 2.9 ? t rdck 8 ? 10 receive data setup to receive clock falling edge 1.0 ? t ckrd 10 ? 12 receive data hold after receive clock falling edge 0.8 ? t pnck 9 ? 10 receive pos/neg setup to receive clock falling edge 0 ? t ckpn 10 ? 13 receive pos/neg hold after receive clock falling edge 3.5 ? note(s): - (1) nominal clock periods are: e3 ? 29.1 ns sts-3c ? 6.4 ns sts-1 ? 19.3 ns d3 ? 22.4 ns e4 ? 7.2 ns (2) duty cycle must be 45/55 at maximum input clock rate.
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-8 conexant 100046c figure 4-3. line interface timing ? internal framers txcki,txckihs tclko txdato 13 9 12 11 10 7 4 2 3 6 5 1 txpos, txneg rxcki,rxckihs rxpos, rxneg rxdati 8 8223_035 table 4-5. parallel interface timing name interval description min max t txcki 1 ? 4 transmit clock period 50 ? t txh 4 ? 5 transmit clock pulse width high (1) 20 ? t cid 1 ? 2 transmit clock in to data out 4.6 16.5 t cdel 1 ? 3 transmit clock in to delineation out 3.9 14.6 t dscr 6 ? 7 transmit disable setup to transmit clock rising edge 0 ? t dhcf 8 ? 9 transmit disable hold after transmit clock falling edge 3.0 ? t rxcki 11 ? 15 receive clock period 50 ? t rxh 11 ? 13 receive clock pulse width high (1) 20 ? t dck 10 ? 11 receive data setup to receive clock falling edge 2.3 ? t ckd 11 ? 14 receive data hold after receive clock falling edge 3.7 ? t dsck 12 ? 13 receive disable setup to receive clock rising edge 3.0 ? t ckds 15 ? 16 receive disable hold after receive clock falling edge 3.0 ? note(s): (1) duty cycle must be 45/55 at maximum input clock rate.
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-9 figure 4-4. parallel interface timing txcki txod txdat[7:0] 13 12 11 10 2 3 6 5 1 txdelo rxcki rxdat[7:0] rxod 478 9 15 16 14 8223_036 table 4-6. overhead port interface timing name interval description min max t ptx, t prx ? transmit or receive clock input period 6.4 ? t tckh 2 ? 4 transmit overhead clock pulse width high 4 t ptx ? t tmtck 1 ? 2 transmit marker valid before transmit clock high 3 t ptx ? t dtck 3 ? 4 transmit overhead data setup before clock falling edge 6.0 ? t tckd 4 ? 5 transmit overhead data hold after clock falling edge 6.0 ? t rck1h 8 ? 9 receive overhead clock1 pulse width high 4 t prx ? t m1rck1 6 ? 8 marker1 valid before clock1 rising edge 3 t prx ? t drck1 7 ? 8 receive overhead data valid before clock1 rising edge 3 t prx ? t rck1d 8 ? 10 receive overhead data valid after clock1 rising edge 2 t prx ? t rck0h 13 ? 14 receive overhead clock0 pulse width high 4 t prx ? t m0rck0 12 ? 13 marker0 valid before clock0 rising edge 3 t prx ? t drck0 11 ? 13 receive overhead data valid before clock0 rising edge 3 t prx ? t rck0d 13 ? 15 receive overhead data valid after clock0 rising edge 2.4 ?
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-10 conexant 100046c figure 4-5. overhead port interface timing tovhclk tmrkr txovh[7:0] rovhclk[1] rmrkr[1] rxovh[7:0] rxovhclk[0] rmrkr[0] 13 14 12 7 10 11 15 6 89 35 1 24 valid 8223_037
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-11 4.3.3 fifo interface timing table 4-7 and figure 4-6 display the timing requirements and characteristics of the fifo port interface. all times are in nanoseconds. table 4-7. fifo port interface timing name interval description phy type 4-7 min phy type 0-3 min t ptx, t prx ? transmit or receive clock input period 6.4 22.4 t wdl 1 ? 2 write strobe low pulse width 4 t prx 2 t prx t wdr 2 ? 4 write strobe recovery time 4 t prx 6 t prx t fws 3 ? 4 full input setup to write strobe falling edge 4.0 4.0 t ivws 5 ? 7 invalid indication stable before write strobe rising edge 3 t prx 2 t prx t dows 6 ? 7 data out valid before write strobe rising edge 3 t prx 2 t prx t wsiv 12 ? 13 invalid indication stable after write strobe rising edge 3 t prx 4 t prx t wsdo 7 ? 8 data out valid after write strobe rising edge 3 t prx 4 t prx t syws 9 ? 12 receive sync valid before write strobe rising edge 3 t prx 2 t prx t wssy 12 ? 14 receive sync valid after write strobe rising edge 3 t prx 4 t prx t err 10 ? 11 write error output valid after write strobe falling edge 1.0 1.0 t rdl 15 ? 17 read strobe low pulse width 4 t ptx 2 t prx t rdr 17 ? 20 read strobe recovery time 4 t ptx 6 t prx t dirs 16 ? 17 data in setup before read strobe rising edge 3.0 3.0 t rsdi 17 ? 18 data in hold after read strobe rising edge 2.0 2.0 t syrs 19 ? 21 transmit sync valid before read strobe rising edge 3 t ptx 2 t prx t rssy 21 ? 22 transmit sync valid after read strobe rising edge 4 t ptx 4 t prx t fsrs 23 ? 26 frame sync valid before read strobe rising edge 2 t ptx 2 t prx t ers 24 ? 26 empty input setup to read strobe rising edge 4.0 4.0
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-12 conexant 100046c figure 4-6. fifo port interface timing rx write rx invalid strobe rx sync marker rx data out full ~ input wrt ~ error output tx read strobe tx sync marker tx data in empty ~ input tx frame sync 1 2471012 9 14 13 5 6 8 3 11 15 17 20 21 25 26 valid sampled on 12th read from end of cell valid 16 18 24 23 22 19 8223_038
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-13 4.3.4 utopia interface timing table 4-8 and figure 4-7 display the timing requirements and characteristics of the utopia interface. all times are in nanoseconds. table 4-8. utopia interface timing name interval description min max t t1 1 ? 4 transmit clock input period 40 ? t t2 1 ? 3 transmit clock high pulse width 16 24 t cff 1 ? 2 transmit clock high to full flag output valid 3 10 t tes 6 ? 7 txenb~ setup to transmit clock rising edge 8 ? t dsu 5 ? 7 txdata, txprty, txsoc setup to transmit clock 8 ? t teh 4 ? 6 txenb~ hold after transmit clock rising edge 1 ? t dh 7 ? 8 txdata, txprty, txsoc hold after transmit clock 1 ? t r1 9 ? 12 receive clock input period 40 ? t r2 9 ? 11 receive clock high pulse width 16 24 t cef 9 ? 10 receive clock high to empty flag output valid 3 10 t cd 14 ? 15 receive clock high to rxdata, rxprty, rxsoc valid 3 10 t res 13 ? 14 rxenb~ setup to receive clock rising edge 8 ? t reh 12 ? 13 rxenb~ hold after receive clock rising edge 1 ?
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-14 conexant 100046c figure 4-7. utopia interface timing 13 4 7 5 8 h1 h2 h3 h4 txclk txdata txprty txsoc txfull ~ txclav txenb ~ 2 6 rxclk 91112 14 15 10 13 rxdata rxprty rxsoc rxempty ~ rxclav rxenb* h1 h2 h3 h4 8223_039
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.3 timing 100046c conexant 4-15 4.3.5 taxi interface timing table 4-9 and figure 4-8 display the timing requirements and characteristics of the taxi interface. all times are in nanoseconds. table 4-9. taxi interface timing name interval description min max t ptx 1 ? 5 transmit clock input period 50 ? t tcl 1 ? 3 transmit clock high pulse width 25 ? t tch 3 ? 5 transmit clock low pulse width 25 ? t clsh 3 ? 4 transmit clock low to strobe output high 3.0 ? t sh 4 ? 6 strobe output pulse width high t ptx /2 12.0 t cssh 2 ? 4 command out setup before strobe high 25 ? t chsh 4 ? 7 command out hold after strobe high 24 ? t dssh 8 ? 9 data out setup before strobe high 22 ? t dhsh 9 ? 10 data out hold after strobe high 25 ? t prx 11 ? 17 receive clock input period 50 ? t rcl 11 ? 14 receive clock low pulse width 25 ? t rch 14 ? 17 receive clock high pulse width 25 ? t ssch 12 ? 14 command strobe setup before clock high 4 ? t csch 13 ? 14 command input setup before clock high 8 ? t shch 14 ? 15 command strobe hold after clock high 0 ? t chch 14 ? 16 command input hold after clock high 5 ? t dsch 18 ? 19 data/violation input setup before clock high 5 ? t dhch 19 ? 20 data/violation input hold after clock high 5 ?
4.0 electrical and mechanical specifications cn8223 4.3 timing atm transmitter/receiver with utopia interface 4-16 conexant 100046c figure 4-8. taxi port interface timing txcki (clk) txout[8] (ci 1) txout[7:0] d[7:0] rxcki (clk) rcvhld (cstrb) rxin[7:0] do [7:0] rxin[8] (vltn) txin (co 1) txclko (strb) hi 13 5 46 9 8 2 7 10 h2 h3 h4 11 14 17 19 12 15 13 16 hi h2 h3 h4 18 20 8223_040
cn8223 4.0 electrical and mechanical specifications atm transmitter/receiver with utopia interface 4.4 mechanical drawing 100046c conexant 4-17 4.4 mechanical drawing the cn8223 is a 160-pin plastic quad flat pack (pqfp) as illustrated in figure 4-9 . figure 4-9. cn8223 160-pin plastic quad flat pack 160 mqfp - 1.60/0.33 form top view bottom view d e e1 d1 b e a2 a a1 1.60 (.063) ref. l s y m b o l all dimensions in millimeters a a1 a2 d d1 e e1 l e b min. ---- 0.25 3.17 30.95 27.90 30.95 27.90 0.60 0.22 nom. ---- ---- 3.37 31.20 28.00 31.20 28.00 ---- 0.65 bsc. ---- max. 4.20 ---- 3.67 31.45 28.10 31.45 28.10 1.15 0.38 8223_041
4.0 electrical and mechanical specifications cn8223 4.4 mechanical drawing atm transmitter/receiver with utopia interface 4-18 conexant 100046c
10046c conexant a-1 a appendix a: transmit fifo port rates this appendix describes the arbitration mechanism used to control and prioritize the transmit fifo port rate. the cn8223 has two options for its atm layer interface: utopia or fifo mode. utopia mode is discussed in the body of the data sheet. fifo mode provides four bidirectional ports. since they operate independently, multiple ports may attempt to send data during the same cell slot. when these collisions occur, the cn8223 implements an arbitration mechanism to select which port will transmit data. the cn8223 combines rate control and priority when selecting a port. first, the rate control circuit determines the eligibility of the port. then the cn8223 arbitrates between eligible ports on a priority basis. this entire process is repeated for each cell slot. a cell which has lost arbitration due to priority may still be determined ineligible for transmission during the next interval. the priority and rate setting of a channel must not be changed once transmission has begun. this will cause unpredictable behavior. it could cause a port to stop transmitting. users can change both priority and rate for ports during an ? idle ? interval. during such an interval, all ports, including unused ports, should assert fifo empty flags. a.1 rate control the cn8223 provides a rate control mechanism to establish fairness. as described in the specification, each port is assigned a maximum rate through a register. this rate is based on a 256-cell slot interval. each port can be allowed to transmit on a percentage of these cell slots. this is accomplished by assigning a rate between 0 and 255 in the tx_rate_xx register. a rate of 0 inhibits transmission on a port, while a rate of 255 allows transmission in any slot. this rate establishes an upper bound on an individual port ? s rate. it does not guarantee a rate for ports sharing a priority with, or at a lower priority than, other active ports. table a-1 lists thresholds for each port ? s tx_rate value. in a given cell slot, these thresholds are compared with the tx_rate_xx register for the port. if the tx_rate value is greater than or equal to the threshold, then the port is eligible to transmit in that slot. otherwise, it is ineligible. note that each port is unique in its transmission characteristics for a given tx_rate value. for instance, with a tx_rate setting of 127 (50 %), port 0 will be eligible for eight cells, then ineligible for eight cells. port 3 will be eligible every other cell. both ports may transmit on 50 % of the cell slots, but the burst length varies.
appendix a: transmit fifo port rates cn8223 a.2 port priority atm transmitter/receiver with utopia interface a-2 conexant 10046c a.2 port priority the user can define a priority for each port. this priority can range from 0 to 3, with 0 being the highest priority. a higher priority port will always preempt one with a lower priority. this priority is programmable for each register in bits 3 ? 2 of the cell_gen_x register. the user can configure multiple ports to be the same priority. within the lowest priority, arbitration is on a ? round-robin ? basis. for example, if port 0 is carrying cbr signals it should be assigned the highest priority. ports 1 and 2, carrying less jitter-sensitive data, can be programmed to a lower priority. port 0 will preempt ports 1 and 2 when data is available. as long as both ports have data available, ports 1 and 2 will alternate transmission in slots where port 0 is not active. only the lowest priority ports should share a priority. round-robin scheduling may break down for multiple ports sharing a priority above a lower priority port. if the cn8223 has been transmitting at priority 1, and a priority 0 port preempts this transmission; that priority 0 port will not share the channel with other ports. it will continue winning arbitration until it no longer has data available. at that time, another priority 0 or lower priority channels will be allowed to transmit. a.3 summary the cn8223 ? s transmit rate shaping is controlled via a user-assigned priority and rate for each fifo port. the cn8223 scheduling attempts to provide a fair arbitration algorithm and to limit burst transmission by a single channel on the line. a system designer should consider each data stream ? s characteristics when choosing the port, priority, and rate to assign.
cn8223 appendix a: transmit fifo port rates atm transmitter/receiver with utopia interface a.3 summary 10046c conexant a-3 slot port 0 port 1 port 2 port 3 0 0000 1 124128 2 241288 3 36132136 4 41288 64 5 5 130 12 192 6 613213672 7 7 134 140 200 8 128 8 64 16 9 129 10 68 144 10 130 12 192 24 11 131 14 196 152 12 132 136 72 80 13 133 138 76 208 14 134 140 200 88 15 135 142 204 216 16 8 641632 17 96620160 18 10 68 144 40 19 11 70 148 168 20 12 192 24 96 21 1319428224 22 14 196 152 104 23 15 198 156 232 24 136728048 25 137 74 84 176 26 138 76 208 56 27 139 78 212 184 28 140 200 88 112 29 141 202 92 240 30 142 204 216 120 31 143 206 220 248 32 64 16 32 1 33 65 18 36 129 34 66 20 160 9 35 67 22 164 137 36 68 144 40 65 37 6914644193 38 70 148 168 73 39 71 150 172 201 40 192249617 41 193 26 100 145 42 194 28 224 25 43 195 30 228 153 44 196 152 104 81 45 197 154 108 209 46 198 156 232 89 47 199 158 236 217 48 72 80 48 33 49 73 82 52 161 50 74 84 176 41 51 75 86 180 169 52 76 208 56 97 53 7721060225 54 78 212 184 105 55 79 214 188 233 56 200 88 112 49 57 201 90 116 177 58 202 92 240 57 59 203 94 244 185 60 204 216 120 113 61 205 218 124 241 62 206 220 248 121 63 207 222 252 249 64 16 32 1 2 65 17 34 5 130 66 18 36 129 10 67 19 38 133 138 slot port 0 port 1 port 2 port 3 table a-1. cell thresholds (1 of 4)
appendix a: transmit fifo port rates cn8223 a.3 summary atm transmitter/receiver with utopia interface a-4 conexant 10046c 68 20 160 9 66 69 2116213194 70 22 164 137 74 71 23 166 141 202 72 144406518 73 145 42 69 146 74 146 44 193 26 75 147 46 197 154 76 148 168 73 82 77 149 170 77 210 78 150 172 201 90 79 151 174 205 218 80 24 96 17 34 81 25 98 21 162 82 26 100 145 42 83 27 102 148 170 84 28 224 25 98 85 2922629226 86 30 228 153 106 87 31 230 157 234 88 152 104 81 50 89 153 106 85 178 90 154 108 209 58 91 155 110 213 186 92 156 232 89 114 93 157 234 93 242 94 158 236 217 122 95 159 238 221 250 96 80 48 33 3 97 81 50 37 131 98 82 52 161 11 99 83 54 165 139 100 84 176 41 67 101 8517845195 slot port 0 port 1 port 2 port 3 102 86 180 169 75 103 87 182 173 203 104 208569719 105 209 58 101 147 106 210 60 225 27 107 211 62 229 155 108 212 184 105 83 109 213 186 109 211 110 214 188 233 91 111 215 190 237 219 112 88 112 49 35 113 8911453163 114 90 116 177 43 115 91 118 181 171 116 92 240 57 99 117 9324261227 118 94 244 185 107 119 95 246 189 235 120 216 120 113 51 121 217 122 117 179 122 218 124 241 59 123 219 126 245 187 124 220 248 121 115 125 221 250 125 243 126 222 252 249 123 127 223 254 253 251 128 32124 129 33 3 6 132 130 34 5 130 12 131 35 7 134 140 132 36 129 10 68 133 3713114196 134 38 133 138 76 135 39 135 142 204 slot port 0 port 1 port 2 port 3 table a-1. cell thresholds (2 of 4)
cn8223 appendix a: transmit fifo port rates atm transmitter/receiver with utopia interface a.3 summary 10046c conexant a-5 136 160 9 66 20 137 161 11 70 148 138 162 13 194 28 139 163 15 198 156 140 164 137 74 84 141 165 139 78 212 142 166 141 202 92 143 167 143 206 220 144 40 65 18 36 145 41 67 22 164 146 42 69 146 44 147 43 71 150 172 148 4419326100 149 4519530228 150 46 197 154 108 151 47 199 158 236 152 168738252 153 169 75 86 180 154 170 77 210 60 155 171 79 214 188 156 172 201 90 116 157 173 203 94 244 158 174 205 218 124 159 175 207 222 252 160 96 17 34 5 161 97 19 38 133 162 98 21 162 13 163 99 23 166 141 164 100 145 42 69 165 101 147 46 197 166 102 149 170 77 167 103 151 174 205 168 224259821 169 225 27 102 149 slot port 0 port 1 port 2 port 3 170 226 29 226 29 171 227 31 230 157 172 228 153 106 85 173 229 155 110 213 174 230 157 234 93 175 231 159 238 221 176 104815037 177 105 83 54 165 178 106 85 178 45 179 107 87 182 173 180 108 209 58 101 181 109 211 62 229 182 110 213 186 109 183 111 215 190 237 184 232 89 114 53 185 233 91 118 181 186 234 93 242 61 187 235 95 246 189 188 236 217 122 117 189 237 219 126 245 190 238 221 250 125 191 239 223 254 253 192 48 33 3 6 193 49 35 7 134 194 50 37 131 14 195 51 39 135 142 196 52 161 11 70 197 5316315198 198 54 165 139 78 199 55 167 143 206 200 176416722 201 177 43 71 150 202 178 45 195 30 203 179 47 199 158 slot port 0 port 1 port 2 port 3 table a-1. cell thresholds (3 of 4)
appendix a: transmit fifo port rates cn8223 a.3 summary atm transmitter/receiver with utopia interface a-6 conexant 10046c 204 180 169 75 86 205 181 171 79 214 206 182 173 203 94 207 183 175 207 222 208 56 97 19 38 209 57 99 23 166 210 58 101 147 46 211 59 103 151 174 212 6022527102 213 6122731230 214 62 229 155 110 215 63 231 159 238 216 184 105 83 54 217 185 107 87 182 218 186 109 211 62 219 187 111 215 190 220 188 233 91 118 221 189 235 95 246 222 190 237 219 126 223 191 239 223 254 224 112 49 35 7 225 113 51 39 135 226 114 53 163 15 slot port 0 port 1 port 2 port 3 227 115 55 167 143 228 116 177 43 71 229 117 179 47 199 230 118 181 171 79 231 119 183 175 207 232 240579923 233 241 59 103 151 234 242 61 227 31 235 243 63 231 159 236 244 185 107 87 237 245 187 111 215 238 246 189 235 95 239 247 191 239 223 240 120 113 51 39 241 121 115 55 167 242 122 117 179 47 243 123 119 183 175 244 124 241 59 103 245 125 243 63 231 246 126 245 187 111 247 127 247 191 239 248 248 121 115 55 249 249 123 119 183 250 250 125 243 63 251 251 127 247 191 252 252 249 123 119 253 253 251 127 247 254 254 253 251 127 255 255 255 255 255 slot port 0 port 1 port 2 port 3 table a-1. cell thresholds (4 of 4)
100046c conexant b-1 b appendix b: acronym list aal atm adaptation layer ais alarm indication signal aps automatic protection switching atm asynchronous transfer mode bip-8 octet bit interleaved parity bom beginning of message cmos complementary metal-oxide semiconductor com continuation of message coset a byte with a specific value cpe customer premise equipment crc cyclic redundancy check eom end of message fas frame alignment signal fcs frame check sequence feac far end alarm control febe far end block error ferf line far end receive failure fifo first in first out hdlc high-level data link control hec header error control isr interrupt service routine lapd link access procedure on the d channel lcv line code violation liu line interface unit loc loss of cell locd loss of cell delineation lof loss of frame los loss of signal lsb least significant bit msb most significant bit nni network-to-network interface nrz non-return to zero oof out of frame pecl pseudo-emitter coupled logic phy physical interface plcp physical layer convergence protocol pmd physical medium dependent
appendix b: acronym list cn8223 atm transmitter/receiver with utopia interface b-2 conexant 100046c poi path overhead identifier pqfp plastic quad flat pack rdi remote defect indication sdh synchronous digital hierarchy smds switched multimegabit data service sonet synchronous optical network [an ansi standard] spe synchronous payload envelope ssm single segment message sts synchronous transport signal taxi transparent asynchronous transmitter/receiver interface uni user-to-network interface utopia universal test and operation physical interface for atm vci virtual channel identifier vpi virtual path identifier
further information: literature@conexant.com 1-800-854-8099 (north america) 33-14-906-3980 (international) web site www.conexant.com world headquarters conexant systems, inc. 4311 jamboree road, p.o. box c newport beach, ca 92658-8902 phone: (949) 483-4600 fax: (949) 483-6375 u.s. florida/south america phone: (727) 799-8406 fax: (727) 799-8306 u.s. los angeles phone: (805) 376-0559 fax: (805) 376-8180 u.s. mid-atlantic phone: (215) 244-6784 fax: (215) 244-9292 u.s. north central phone: (630) 773-3454 fax: (630) 773-3907 u.s. northeast phone: (978) 692-7660 fax: (978) 692-8185 u.s. northwest/pacific west phone: (408) 249-9696 fax: (408) 249-7113 u.s. south central phone: (972) 733-0723 fax: (972) 407-0639 u.s. southeast phone: (919) 858-9110 fax: (919) 858-8669 u.s. southwest phone: (949) 483-9119 fax: (949) 483-9090 apac headquarters conexant systems singapore, pte. ltd. 1 kim seng promenade great world city #09-01 east tower singapore 237994 phone: (65) 737 7355 fax: (65) 737 9077 australia phone: (61 2) 9869 4088 fax: (61 2) 9869 4077 china phone: (86 2) 6361 2515 fax: (86 2) 6361 2516 hong kong phone: (852) 2 827 0181 fax: (852) 2 827 6488 india phone: (91 11) 692 4780 fax: (91 11) 692 4712 korea phone: (82 2) 565 2880 fax: (82 2) 565 1440 europe headquarters conexant systems france les taissounieres b1 1681 route des dolines bp 283 06905 sophia antipolis cedex france phone: (33 4) 93 00 33 35 fax: (33 4) 93 00 33 03 europe central phone: (49 89) 829 1320 fax: (49 89) 834 2734 europe mediterranean phone: (39 02) 9317 9911 fax: (39 02) 9317 9913 europe north phone: (44 1344) 486 444 fax: (44 1344) 486 555 europe south phone: (33 1) 41 44 36 50 fax: (33 1) 41 44 36 90 middle east headquarters conexant systems commercial (israel) ltd. p.o. box 12660 herzlia 46733, israel phone: (972 9) 952 4064 fax: (972 9) 951 3924 japan headquarters conexant systems japan co., ltd. shimomoto building 1-46-3 hatsudai, shibuya-ku, tokyo 151-0061 japan phone: (81 3) 5371 1567 fax: (81 3) 5371 1501 taiwan headquarters conexant systems, taiwan co., ltd. room 2808 international trade building 333 keelung road, section 1 taipei 110, taiwan, roc phone: (886 2) 2720 0282 fax: (886 2) 2757 6760 0 . 0 sa l es offi ces

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